REGISTER
CONVENTIONS
Frequent
use
is
made
in
this
manual
of parenthesized
register
names.
This
is
shorthand notation for the expression
lithe
contents of
register
II
For
example,
"Branch
to
(P)
means
"Branch
to the address indicated
by
the contents of the
program
parcel counter, P."
Extensive
use
is
also
made
of subscripted designations for the
A,
B,
S,
T,
and
V
registers.
For
example, "Transmit (Tjk) to Si"
means
"Transmit
the contents of the T
register
specified
by
the jk designators to the S
register
specified
by
the i designator.
II
In
this
manual,
register
bit
positions are
numbered
from
left
to
right
starting
with
bit
O.
Bit
63
of
an
S,
V,
or T
register
value represents
the
least
significant
bit
in the operand. Bit
23
of
an
A or B
register
value represents the
least
significant
bit
in the operand.
When
a
power
of
two
is
meant
rather than a
bit
position,
it
is
referred to
as
2
n
,
where
n
is
the
power
of
two.
OPERATING
REGISTERS
Operating
registers
are a primary
programmable
resource of the
CRAY-I.
They
enhance
the
speed
of the system
by
satisfying
the
heavy
demands
for
data
that
are
made
by
the functional
units.
A single functional unit
may
require
one
to three operands per clock period
and
may
deliver
results
at
a
rate
of
one
per clock period.
Moreover,
multiple functional units
can
be
in
use
concurrently.
To
meet
these requirements, the
CRAY-I
has
five
sets
of
registers;
three primary
sets
and
two
intermediate
sets.
The
three primary
sets
of
registers
are vector,
scalar,
and
address designated
in
this
manual
as
V,
S,
and
A,
respectively.
These
registers
are considered
primary because functional units
can
access
them
directly.
For
the
scalar
and
address
registers,
an
intermediate level of
registers
exists
which
is
not accessible to the functional
units.
These
registers
act
as
buffers
for the primary
registers.
Block
transfers
are possible
between
these
registers
and
memory
so
that
the
number
of
memory
references required for
scalar
and
address operands
is
greatly reduced.
The
intermediate
registers
that
support
scalar
registers
are referred to
~s
T
registers.
The
inter-
mediate
registers
that
support the address
registers
are referred to
as
B
registers.
2240004
3-3
E
To Next Page
Loading...