COMPUTATION SECTION
INTRODUCTION
The
computation section (figure 3-1) consists of
an
instruction control
network, operating
registers,
and
functional
units.
The
instruction
control
network
performs
all
decisions related to instruction issue
and
coordinates the
activities
for the three types of processing, vector,
scalar,
and
address. Associated with
each
type of processing are
registers
and
functional units
that
support the processing
mode.
For
vector processing, there are: a
set
of 64-bit 64-element
registers,
3
three functional units dedicated solely to vector applications,
and
three
floating point functional units supporting
both
scalar
and
vector operations.
For
scalar
processing, there are
two
levels of 64-bit
scalar
registers
and
four functional units dedicated solely to
scalar
processing in addition
to the three floating point units shared with the vector operations.
For
address processing, there are
two
levels of 24-bit
registers
and
two
integer arithmetic functional
units.
Vector
and
scalar
processing
is
performed
on
data
as
opposed
to address
processing
which
operates
on
internal control information
such
as
addresses
and
indexes.
The
flow
of data in the computation section
is
generally
from
memory
to
registers
and
from
registers
to functional
units.
The
flow
of
results
is
from
functional units to
registers
and
from
registers
to
memory
or
back
to functional units.
Data
flows
along
either
the
scalar
or vector
path depending
on
the
mode
of processing
it
is
undergoing.
An
exception
is
that
scalar
registers
can
provide
one
of the operands required for vector
operations performed in the vector functional
units.
The
flow
of address information
is
from
memory
or
from
control
registers
to
address
registers.
Information in the address
registers
can
then
be
distributed
to various parts of the control
network
for
use
in controlling the
scalar,
vector,
and
I/O
operations.
The
address
registers
can
also supply operands
to
two
integer functional
units.
The
units generate address
and
index
information
and
return the
result
to the address
registers.
Address
information
can
also
be
transmitted to
memory
from
the address
registers.
2240004
3-1
E
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