INSTRUCTION
ISSUE
AND
CONTROL
This section describes the instruction buffers
and
registers
involved
with instruction issue
and
control.
Fi~ure
3-6
illustrates
the general
flow
of
instruction
parcels through the
registers
and
buffers.
r
I
3
r
I
2
I
I
1
I
at
_
,0
I
I
I
I
1
t
NIP
H_---.C
;,.-P
__
L
__
~.
L..t
Execution
17
P
REGISTER
-
LIP
-
_..-.._
....
-
--
--.
r-
Instruction
Buffers
Figure 3-6. Relationship of
instruction
buffers
and
registers
The
P
register
is
a 22-bit
register
which
indicates the next parcel
of
program
code
to enter the next
instruction
parcel
(NIP)
register
in a
linear
program
sequence.
The
upper
20
bits
of the P
register
indicate the
word
address for the
program
word
in
memory.
The
lower
two
bits
indicate the parcel within the
word.
The
content of the P .
register
is
normally
advanced
as
each
parcel successfully enters the
NIP
register.
The
value in the P
register
normally corresponds to the
parcel address for the parcel currently
moving
to the
NIP
register.
2240004
3-32
E
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