The
NIP
register
is
not master
cleared.
An
undetermined
instruction
may
issue
during the master
clear
interval
before
the
interrupt
condition
blocks data
entry
into
the
NIP
register.
LIP
REGISTER
The
LIP
(lower instruction parcel)
register
is
a 16-bit
register
which
holds the
lower
half of a two-parcel instruction
at
the time the
two-
parcel instruction issues
from
the
CIP
register.
INSTRUCTION
BUFFERS
There
are four instruction buffers in the
CRAY-1,
each
of
which
holds
64
consecutive 16-bit instruction parcels (figure 3-7). Instruction parcels
are held in the buffers prior to being delivered to the
NIP
or
LIP
registers.
Bank
0
1 4
5 6
7
---
----
---
---
2
10
__
_
11
__
12
__
_13_
3
14
_15
__
16
__
17
---
---
4
20
_
£1
__
22
23
---
---
---
5
24
_
£5
__
26
27
---
---
---
6
30
31
32
33
---
-...-
--
---
---
7
34
35
36
37
---
----
------
lOs
40
41
42
43
---
----
118
44
45
46
47
---
----
---
---
12
8
50
51
52
53
---
----
---
---
13
s
54 55
56
57
---
----
14s
60
61
62
63
Buffer 3
---
----
------
15
s
64
65
66 67
Buffer
2
---
----
16
s
70
71
72
73
Buffer 1
---
_a-
__
---
---
17s
74
75
76
77
Buffer 0
Figure
3-7
Instruction buffers
2240004
3-34
E
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