The
beginning
instruction
parcel in a buffer
always
has
a parcel address
that
is
an
even
multiple of
lOOs.
This allows the
entire
range of
addresses for
instructions
in a buffer to
be
defined
by
the high-order
16
bits
of the beginning parcel address.
For
each
buffer, there
is
a 16-bit
beginning address
register
that
contains
this
value.
The
beginning address
registers
are scanned
each
clock period.
If
the
high-order
18
bits
of the P
register
match
one
of the beginning addresses,
an
in-buffer condition
exists
and
the proper instruction parcel
is
selected
from
the instruction buffer.
An
instruction parcel to
be
executed
is
normally sent to the
NIP.
However,
the
second
half of a
two-parcel
instruction
is
blocked
from
entering the
NIP
and
is
sent to
the
LIP,
instead,
and
is
available
when
the upper
half
issues
from
the
CIP.
At
the
same
time, a blank parcel
is
entered into the
NIP.
On
an
in-buffer condition,
if
the instruction
is
in a
different
buffer
than the previous
instruction,
a
change
of buffers occurs necessitating a
two
clock period delay of issue.
An
out-of-buffer condition
exists
when
the high-order
18
bits
of the P
register
do
not
match
any
instruction
buffer beginning address.
When
this
condition occurs,
instructions
must
be
loaded into
one
of the
instruction
buffers
from
memory
before execution
can
continue.
The
instruction buffer
that
receives the instructions
is
determined
by
a
two-
bit
counter.
Each
occurrence of
an
out-of-buffer condition causes the
counter to
be
incremented
by
one
so
that
the buffers are selected in
rotation.
Buffers are loaded
from
memory
four
words
per clock period,
an
operation
that
fully
occupies
memory.
The
first
group
of
16
parcels delivered to
the buffer
always
contains the
instruction
required for execution.
For
this
reason, the branch out of buffer time
is
a constant
14
clock
periods~
The
remaining groups
arrive
at
a
rate
of
16
parcels per clock period
and
circularly
fill
the buffer.
t Refer to 8
Bank
Phasing Option, section
5.
2240004
3-35
E
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