An
instruction
buffer
is
loaded with
one
word
of
instructions
from
each
of the
16
memory
banksJ
The
first
four instruction parcels residing in
an
instruction buffer are
always
from
bank
O.
Figure
3-7
illustrates
the organization of pRrcels
and
words
in
an
instruction buffer.
An
exchange
sequence voids the
instruction
buffers
by
setting
their
beginning address
registers
to
all
ones. This prevents a
match
with the
P
register
and
causes
one
of the buffers to
be
loaded.
Both
forward
and
backward
branching
is
possible within the buffers. A
branch
does
not cause reloading of
an
instruction
buffer
if
the instruc-
tion being branched to
is
within
one
of the buffers. Multiple copies of
instruction
parcels cannot occur in the instruction buffers.
Because
instructions are held in
instruction
buffers
prior
to
issue,
no
attempt
should
be
made
to dynamically
modify
instruction
sequences.
As
long
as
the unmodified
instruction
is
in
an
instruction
buffer, the modified
instruction
in
memory
will not
be
loaded into
an
instruction
buffer.
Although
optimization of
code
segment
lengths for
instruction
buffers
is
not a
prime
consideration
when
programming
the
CRAY-1,
the
number
and
size of the buffers
and
the
capability
for both forward
and
backward
branching
can
be
used
to
good
advantage.
Large
loops containing
up
to
256
consecutive instruction parcels
can
be
maintained in the four buffers or
as
an
alternative,
one
could
have
a
main
program
sequence in
one
or
two
of the
buffers
which
makes
repeated
calls
to short subroutines maintained in the
other buffers.
The
program
and
subroutines
remain
in the buffers undisturbed
as
long
as
no
out-of-buffer condition causes a buffer to
be
reloaded.
t Refer
to
8-bank phasing
option,
section
5.
2240004
3-36
E
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