Cray CRAY-1 - F Register

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,

n+2

Bit

36

n+2

Bit

37

n+2

Bit

38

Correctable

memory

error

mode

flag.

When

this

bit

is

set,

interrupts

on

correctable

errors

are enabled.

Floating point

error

mode

flag.

When

this

bit

is

set,

interrupts

on

floating

point

errors

are enabled.

Uncorrectable

memory

error

mode

flag.

When

this

bit

is

set,

interrupts

on

uncorrectable

memory

errors

are

enabled.

n+2

Bit

39

Monitor

mode

flag.

When

this

bit

is

set

and

the Monitor

Mode

Interrupt

Option

is

not

present,

all

interrupts

other

than

memory

errors

are

inhibited.

When

the

Moni-

tor

Mode

Interrupt

Option

is

present,

this

bit

serves

as the monitor

mode

select

flag.

When

it

is

set,

monitor

mode

1

or

monitor

mode

2

is

selected depending

on

the

state

of the

interrupt

monitor

mode

select

bit

(Bit

39

of n+1).

The

interrupt

monitor

mode

select

bit

determines

which

interrupt

flags

can

be

set

while

the

CPU

is

in monitor

mode.

Bit

37

of

n+2,

the

floating

point

error

mode

select,

can

be

set

or cleared

during the execution

interval

for a

program

through use

of

the

0021

and

0022

instructions,

respectively.

Bits

38

and

39

of

n+2

are not

altered

during the execution

interval

for the exchange package. Either of these

bits

can

be

altered

only

when

the exchange package

is

inactive

in

memory.

F

REGISTER

The

F

(flag)

register

is

a

nine-bit

register

that

contains

part

of the

exchange package for the

currently

active

program. This

register

contains

nine flags

which

are

individually

identified

with the exchange

packa~e

in

figure 3-8. Setting

any

of

these flags causes

interruption

of

the

program

execution.

When

one

or

more

flags are

set,

a request

interrupt

signal

is

sent to

initiate

an

exchange sequence.

The

content

of

the F

register

is

stored along with the

rest

of

the exchange package

and

the monitor

program

can

analyze the nine flags for the cause

of

the

interruption.

Before the

monitor

program

exchanges

back

to the package,

it

may

clear

the flags in

the F

register

area

of

the package.

If

any

of the

flag

bits

is

set

during

the

transfer

of

the exchange package to the

CPU,

another exchange will

occur immediately.

2240004

3-39

E

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