Cray CRAY-1 - Page 74

I
I
n
n+1
n+2
n+ 3
n + 4
n + 5
n + 6
n .. 7
n .. 8
n+-9
10 12 16 18
31 36 40
63
AO
AI
A2
A3
A4
AS
A6
A7
50
51
52
n+IO ~ ____________________________________________ ~
53
n + II
54
n+12 L---------------------------------------------~
55
n+13 ~--------------------------------------------__1
56
n+14 ~--------------------------------------------~
57
n+15 L- ____________________________________________ ~
Registe_!:.~
S Syndrome bits
RAB Read address for error
(where B is bank)
P Program address
BA Base address
LA Limit address
XA Exchange address
VL Vector length
M -
Modes
I n+ 1 39 I nterr~-~~~o;i tor mode t
n+2 36 Interrupt on correctable
memory error
n+2 37 Interrupt on floating point
error
n+2 38 Interrupt on uncorrectable
memory error
n+2 39 Monitor mode
~Jl~
L:- ___ E rr~r. typ~ .. (l?tt~ __ il._'._.~._~f __ .!l)
10 Uncorrectable memory
n+3 31 Programmable clock interrupttt
01 Correctable memory
~~~cif!lode (I:?; ts J9.~J! __ Q_f..l!l
00 Scalar
01 I/O
10 Vector
11 Fetch
n+3 32 MCU interrupt
n+3 33 Floating point error
n+3 34 Operand range error
n+3 35 Program range error
n+3 36 Memory error
n+3 37 I/O interrupt
n+3 38 Error exit
n+3 39 Normal exit
t Supports Monitor Mode Interrupt option.
tt Supports Programmable Clock option.
Figure 3-8.
Exchange package
2240004
3-38
E