Cray CRAY-1 - Memory Address; 16 Banks; Vector Memory Rate * 80 X 10 6 References Per Second

I
MEMORY ADDRESSING
A word
in a 16-bank memory
is addressed in 20 bits as
shown in
figure 5-1.
The
low order four
bits specify one of the
16 banks.
The next field
specifies an address within
the
chip.
The
upper bits specify one of the chips on
the
module.
Figure 5-1.
Memory address; 16 banks
A word in a 1/2 million word 8-bank memory is addressed in 19 bits (not
shown) :
The low order !hree bits specify one of the 8 banks
The next field specifies an address within the chip
The upper bits specify one of the chips on the module.
Addressing a
full million words with 8-bank phasing is possible. In this
case, the right/left bank select switch determines only whether the lower
half of memory or the upper half is selected first in the addressing scheme
by inverting or not inverting bit 219. Under program control, bit 2
19
selects the lower or upper half of memory because the bit is injected at
bit 21 of the memory address.
SPEED CONTROL
For 176 and 177 instructions, (Ak) determines speed control (table 5-1).
Table 5-1. Vector memory rate * 80 x 10
5
references per second
Phasing Increment
or multiple
1-3
4
5-7
8
9-11
12
13-15
16
8-bank
1 1/2
1 1/4 1
1/2 1 1/4
16-bank 1 1
1
1/2
1
1
1
1/4
2240004
5-4
E