I
For
eight
banks, incrementing 8 places causes successive references in the
same
bank
so
that
a
word
is
transferred
every 4
CPs.
If
(Ak)
is
incremented
by
4,
an
8-bank
memory
transfers
words
every 2
CPs.
8-BANK
PHASING
OPTION
The
8-bank phasing option
makes
possible a system consisting of one-half
million
words
arranged in only
eight
banks.
Any
16-bank system
can
exercise
the option
by
replacing
two
modules
and
setting
the
bank
select
switch
to
the
left
or
right
banks. A system constructed with only
eight
banks
of
modules
but with
all
12
of
its
columns
can
be
upgraded to a 16-bank
full
million
words
by
completing the remaining banks.
The
effect
of
8-bank phasing
on
instruction
fetches
is
a predictable
increase of
4 clock periods for
filling
an
instruction
buffer. Otherwise,
the
amount
of
performance degradation for 8
banks
as
compared
with
16
banks
is
not
readily
predictable
since
it
largely
results
from
an
increase
of
memory
conflicts
for vector
memory
references.
For
other
differences,
refer
to the preceding paragraphs
on
MEMORY
ADDRESS-
ING
and
SPEED
CONTROL.
MEMORY
PARITY
ERROR
CORRECTION
An
error
correction
and
detection network
between
the
CPU
and
memory
assures
that
the data
written
into
memory
can
be
returned to the
CPU
with
consistent
precision.
(Refer to figure 5-2. )
The
network operates
on
the basis
of
single
error
correction,
double
error
detection
(SECDED).
If
one
bit
of a data
word
is
altered,
the
single
error
alteration
is
automatically corrected before passing the data
word
to the computer.
If
two
bits
of the
same
data
word
are
altered,
the double
error
is
detected but not
corrected.
In
either
case,
the
CPU
may
be
inter-
rupted depending
on
interrupt
options
selected
to prevent
incorrect
data
from
contaminating a job.
For
three or
more
bits
in
error,
results
are
ambiguous.
2240004
5-5
E
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