Cray CRAY-1 - Page 165

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A scalar conflict in rank A (CP 2 of a scalar instruction) causes a hold
storage
on this instruction for three clock periods. At the same time,
a hold issue signal blocks the issue of another
scalar reference instruc-
tion. The only memory conflict that may occur in rank A is a scalar ref-
erence conflicting with a previous I/O reference. It is not possible for
a scalar to conflict with a scalar in rank A because it takes two clock
periods to issue a
scalar reference instruction.
J\ scalar conflict in rank B (CP 3) causes a hold storage on this instruc-
tion for two clock periods. Also, a hold issue signal blocks issue of
another
scalar reference instruction.
A scalar conflict in rank C (CP 4) causes a hold storage on this instruc-
tion for one clock period. There is also a hold issue signal, which
blocks issue of another scalar reference instruction.
Under normal operating conditions on codes performing a mix of vector and
scalar instructions, the memory access will support four disk and three
interface channels without degrading the CPU computation rate. However,
a single program requiring memory access continuously will be measurably
degraded
by maximum I/O transfer conditions. This is caused by the delays
imposed on the issue of vector memory instructions because block transfers
require memory quiet before issue.
The memory is organized into 8 or 16 interleaved banks to minimize memory
conflicts and to exploit the speed of the memory chip. Each bank occupies
a chassis
and contains 72 modules. Each module contributes one data or
check
bit to each 72-bit word in the bank; a memory word consists of 64
data bits and 8 check bits.
The 16-bank phasing is standard on the CRAY-l; 8-bank phasing, allowing
a
maximum memory size of 1/2 million owrds, can be accomplished by replac-
ing
two modules and setting the bank select switch to the left or the
right banks. This option is available on any 16-bank memory machine.
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