Cray CRAY-1 - Page 164

,
slowing or disallowing the vector operations that would be affected by the
slowed
memory referencing rate. The vector logic identifies 1/4 speed
(4 CP), 1/2 speed (2 CP), and full speed (ICP) data rates from memory.
Fetch operations require memory to be quiet before referencing memory.
Once the fetch request is honored, all other memory references are blocked.
Exchange operations require memory to be quiet before referencing memory.
After the exchange has issued, all other memory references are blocked.
Scalar and I/O memory references are examined in three registers for
possible
memory conflicts. These three registers contain the lower 4 bitst
of each of the referenced memory addresses. These registers plus the ad-
dress
register represent the 4 CPs between referencing anyone bank. The
first bank is rank A, the second is rank B, and the third is rank C. At
each clock, the contents of the registers are shifted down one rank until
they are discarded unless a conflict arises, in which case the conflicting
address is held in rank B until the conflict is resolved.
I/O requests are tested against ranks A, B, and C. Coincidence with rank
A, B, or C disallows the request. An I/O request that is disallowed must
wait eight clock periods before it can request again.
The following conditions must be present for an I/O memory request to be
processed:
1.
I/O request
2. No coincidence in rank A, B, or C
3. No scalar memory reference instruction in clock period two of
its sequence (scalar priority over I/O)
4.
No fetch request
5.
No 176, 177, or 034 through 037 instruction in progress
6.
No exchange sequence
7. No 033 request (not a memory conflict)
Scalar instruction memory requests are tested in ranks A, B, and C for
memory conflicts. Scalar instructions have priority over I/O requests
arriving at memory in the same clock period.
t
See eight-bank phasing.
2240004
5-2
E