Cray CRAY-1 - CRAY-1 Memory Access

MEMORY SECTION
INTRODUCTION
--~-"- ------- .-- .-
..t.
The memory for the CRAY-l normally consists of 16 banksl of bi-polar LSI
memory. Three memory sizes are available:
262,144 words,
524,288 words, or
1,048,576 words.
The banks are independent of each other.
MEMORY CYCLE TIME
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The memory cycle time is four clock periods (50 nsec). The access time,
that is, the time required to fetch an operand from memory to an opera-
tional
register is 11 clock periods (127.5 nsec).
MEMORY ACCESS
The memory of the CRAY-l Computer System is shared by the computation
section
and the I/O section. A single port access is provided.
5
Because of the interleaving scheme used to address the independent banks,
it is possible to reference memory every clock period with a new request.
It is not possible, however, to reference anyone bank sooner than its
4 CP cycle time. Trying to reference a bank more often than every 4 CPs
causes memory conflicts. These conflicts are handled in an orderly, pre-
dictable manner.
All block transfers require memory to be quiet before issuing. Once
issued, they block all other memory requests. Multiple block transfers
cannot issue without allowing one waiting I/O reference to complete. The
maximum duration of a lockout caused by block transfers is one block length.
Vector block
transfers may conflict with themselves. Therefore, the vector
logic provides for
identifying these conditions (speed control) and for
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t See eight-bank phasing.
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