Cray CRAY-1 - Page 69

The P register is entered ytith new data on an instruction branch or
on an exchange sequence. It is then advanced sequentially until the
next branch or exchange sequence.
The value in the P register is
stored directly into the terminating exchange package during an
exchange sequence.
The P register is not master cleared. An undetermined value is stored in
the terminating
exchange package at address zero during the dead start
sequence.
CIP REGISTER
The CIP (current instruction parcel) register is a I6-bit register
which holds the instruction waiting to issue. If this instruction
is a two-parcel instruction, the CIP register holds the upper half
of the instruction and the LIP holds the lower half. Once an
instruction enters the CIP register, it must issue. Issue may be
delayed until previous operations have been completed but then the
current
instruction waiting for issue must proceed. Data arrives
at the CIP register from the NIP register. The indicators which make
up the instruction are distributed to all modules which have mode
selection requirements when the instruction issues.
The control flags associated with the CIP register are generally master
cleared.
The register itself is not and an undetermined instruction will
issue during the master
clear sequence.
NIP REGISTER
The NIP (next instruction parcel) register is a IE-bit register
which holds a parcel of program code prior to entering the CIP
register. A parcel of program code which has entered the NIP
register must be executed. There is no mechanism to discard it.
2240004
3-33
E