I
I
MEMORY
SECTION
The
memory
for the
CRAY-l
normally consists of
16
bank~'
of bi-polar
LSI
memory.
Three
memory
size options are available: 262,144 words,
524,288
words, or 1,048,576
words.
Each
word
is
72
bits
long
and
consists
of
64
data
bits
and
8
check
bits.
The
banks
are independent of
each
other.
Sequentially addressed
words
reside
in
sequential banks.
The
memory
cycle
time
is four clock periods
(50
nsec).
The
access time,
that
is,
the
time
required to fetch
an
operand
from
memory
to a
scalar
register
is
11
clock
periods (137.5 nsec).
The
maximum
transfer
rate
for
B,
T,
and
V
registers
is
one
word
per
clock period.
For
A
and
S
registers,
it
is
one
word
per
two
clock
periods. Transfers of
instructions
to the
instruction
buffers occur
at
a
rate
of
16
parcels (four
words)
per clock period.
Thus, the
high
speed of
memory
supports the requirements of
scientific
applications while
its
low
cycle
time
is
well suited to
random
access
applications.
The
phased
memory
banks
allow
high
communication
rates
through the
I/O
section
and
provide
low
read/store times for vector
registers.
INPUT/OUTPUT
SECTION
Input
and
output
communication
with the
CRAY-l
is
over
12
full
duplex
16-bit channels. Associated with
each
channel are control lines
that
indicate the presence of data
on
the channel (ready), data received
(resume), or
transfer
complete (disconnect).
The
channels are divided into four channel groups. A channel
group
consists of
either
six input paths or six output paths.
The
four
channel groups are scanned sequentially for
I/O
requests
at
a
rate
of
one
channel
group
per clock period.
The
channel
group
will
be
reinterrogated
four clock periods
later
whether
any
I/O
request
is
pending in the
channel
or not.
If
more
than
one
channel of the channel
group
is
active,
the
requests are resolved
on
a
priority
basis.
The
request
from
the lowest
numbered
channel
is
serviced
first.
t
See
8-Bank
Phasing Option, section
5.
2240004
1-5
E
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