CPU Control Module Theory of Operation
2 - 4 0070-10-0441 Passport 2®/Passport 2 LT™ Service Manual
The Flash devices are provided a buffered reset by FET Q9 and associated components. This
reset signal is generated from the MPC860T's HRESET. The reset is required to place the
Flash devices' internal state machine in a known state after power is applied for either
fetching or programming.
Bank decoding is performed by a sub-circuit of CPLD U1, and is dependent on the state of
Address line A(8) in conjunction with active CS0*.
2.1.6 DRAM Memory, U8, U10
This memory is made up of two 4M x 16 devices which form a 4M x 32 byte memory array.
These memories are volatile as well as requiring special timing and control signals, RAS*
and CAS* to operate. The type of DRAM is Fast Page Mode with an access time of 50nsec.
The special timing signals required are generated by an internal timing circuit contained in
the MPC860T. This timing generator is called Universal Programmable Machine A (UPMA).
There is another one called Universal Programmable Machine B (UPMB), which is not used.
The universal programmable machines are flexible interfaces that connect to a wide range of
memory devices, such as Fast Page Mode Dram's. At the heart of the UPM is an internal
memory RAM that specifies the logical value driven on the external memory controller pins
for each clock cycle. Each word in the RAM array provides bits that allow a memory access
to be controlled with a resolution of one quarter of the external bus clock period on the byte-
select and chip-select lines. The RAM array contains 64, 32 bit words. The internal signal
timing generator loads the RAM word from the RAM array to drive the general-purpose lines,
byte-selects, and chip-selects.
The UPM RAM array is to be loaded by the board support software at power-on. The
following is UPM RAM array values to support 50nsec Fast Page Mode DRAM with the
processor operating at 50MHz.
UPMA Initializations for 50nsec DRAM's @ 50Mhz.
2.1.7 RTC with CPU Supervisor
The Real Time Clock module, BQ4847, integrates a time of day clock, a 100 year calendar,
a CPU supervisor, a battery and a crystal in a 28 pin DIP module. There are 16 registers
which contain real-time clock and alarm functions. The clock has an accuracy of +/-1 minute
per month. The duration of the power-on reset signal is 100ms min. The MPC860T requires
only 3us minimum.
Using the BQ4747’s CE out and battery voltage out, Vout, static RAM U9 is made to be non-
volatile. The internal battery powers the real time clock and maintains SRAM information in
the absence of system voltage. When an out of tolerance (4.3 to 4.5 volt) condition is
detected the BQ4747 generates an interrupt warning. The interrupt is fed to the IRQ0 NMI
input on the MPC860T. This will allow 90us min. to save any data to the non-volatile SRAM.
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