Passport 2®/Passport 2 LT™ Service Manual 0070-10-0441 2 - 5
Theory of Operation CPU Control Module
2.1.8 Battery Backup SRAM, U9
The SRAM is configured as 128K x 8 bits and is used to store system configuration settings.
These settings are required to be non-volatile, therefore the SRAM is battery backed-up when
system power is removed. This is achieved by the battery output that is contained in the RTC
module, U7, and is outputted on pin 1.
2.1.9 Dual Port RAM, U604, U777
There is a high speed 2K x 8 Dual Port RAM with internal logic for inter-processor
communications. The device has two independent ports with separate control, address, and
I/O pins that permit independent asynchronous access for reads to any location in memory.
However, an attempt by one of the processors to access ('READ' or 'WRITE') an address
location at the same time the other processor is attempting to access the identical location
results in a 'BUSY' condition, and results in a 'write inhibit' to whichever side asserted the
chip enable last (Not all such accesses will be 'WRITE LEFT/WRITE RIGHT'). The 'BUSY'
condition is not reported to either processor in this implementation, and therefore, the
software must be designed so as to avoid the possibility of concurrent access by both
processors to an identical location.
The device is used for inter-communication between the main processor, MPC860T (U2) and
the communication processor MCF5282 (U22). Refer to the Module Bus Protocol
Specification (See Appendix).
The implementation uses the interrupt function. There are two flags, one for each side of the
DPRAM. A memory location within the DPRAM is assigned to each flag. The interrupt line to
the MPC860T is asserted when the MCF5282 writes to memory location CS1 + 0x0000
07FE. In order to reset this interrupt flag, the MPC860T must access memory location CS3
+0x0000 0FFE. Similarly, the interrupt line to the MCF5282 is asserted when the MPC860T
writes to memory location CS3 + 0x0000 0FFF. In order to reset this interrupt flag, the
MCF5282 must access memory location CS1 + 0x0000 07FF. Please note that in addition to
the flag functions described above, these two addresses are valid memory locations and may
be used for message passing.
A 5V to 3.3V conversion is performed with U777. This is to protect the DPRAM, which
cannot have 5V logic on any of its pins, even if it is not accessing the bus.
2.1.10 Audio Generator Circuit, U12, U27, U13
The audio circuit is composed of three integrated circuits, Wave Table Music Synthesizer, a
24 Bit Stereo D/A Converter and a one watt Power Amplifier.
U12 is a complete general MIDI wave table synthesizer on a single integrated circuit. The
MIDI interpreter, synthesis engine, effects processing, and all memory are included on chip.
The device receives a standard serial MIDI data stream at 31.25 +/-1% kbits/s, and outputs
a stereo 16 bit digital audio stream at 44.1kHz.
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