Datascope Passport 2 - Analog to Digital Converter; Microcontroller and Data Processing

Passport 2®/Passport 2 LT™ Service Manual 0070-10-0441 2 - 13
Theory of Operation Front End Module
2.2.4 Analog to Digital Converter
The MAX147 ADC is operated in the single ended bipolar mode, with external clock. The
control byte sent to the converter by the QSPI is %1mm, where mm is the ADC multiplexer
channel. Since the entire analog signal path is “floated” on the +2.5 volt reference, the ADC
analog common is referenced to this voltage also. The ADC therefore produces signed output
data for analog inputs corresponding to nominally ±1.25 volts around the +2.5 volt
reference. The ADC results are read into the QSPI receive RAM as words, and are left-
justified. That is, the sign bit of the ADC data is the msb of the word, and the 12 bit ADC
data is padded with 4 trailing zeros. The ADC regards the leading “1" in the command byte
as a synchronization bit. Therefore, the output data justification is controlled by the
justification of the command byte within the word transmitted by the QSPI.
2.2.5 Microcontroller and Data Processing
The Front End is controlled by U224, a Motorola MCF5282 microcontroller operating in the
single-chip mode. The board pulls RCON* high, which causes the processor to enter this
mode as it comes out of reset. The internal 64.0MHz clock is generated by the internal
synthesizer from a 8.000 MHz reference crystal. The crystal operates with roughly sinusoidal
waveforms, and therefore generates less EMI than a square-wave oscillator module. To
further minimize EMI and avoid the need for external pull up resistors, all unneeded dynamic
I/O pins are set as outputs and disabled. This is performed by programming all the unused
general purpose I/O pins as outputs at initial software boot up. This also helps reduce power
dissipation. The other default values that are set by RCON* high are: boot port size - internal
(32 bits); pad driver load - full drive strength; PLL reference - crystal; boot select - internal boot
device; PLL mode - normal.
Two SCI ports are used. The first SCI port is used to interface to the host communication
controller across the isolation barrier via the opto-couplers. The processor lies on the patient
isolated side of the barrier, and communicates using the serial module bus. The required SCI
baud rate is 500K baud. A second SCI is used to communicate to the SpO
2
boards. The
third SCI is used for debugging purposes.
Power for the core is supplied by a +3.3VD switching power supply. Power for the internal
A/D converter is supplied by a +5V linear regulator. The processor is resetable by a hard
reset using several methods: 1) on power up; 2) generated locally by monitoring a voltage
supervisory chip; and 3) the provision is made to have the module bus reset from the CPU
side sent across the isolation barrier optocouplers, and then go to the microcontroller reset
pin causing a hard reset. The Communications Processor will reset all the modules on the
module bus at the beginning of its operation (after its own initialization).
A general purpose timer is used for several functions. One input capture channel is used for
the pacer detection edge capture. Two output compare channels are used to implement the
38.4KHz respiration clock. The real time ECG trigger pulse is used with a general purpose
I/O.
The periodic interrupt timer has the capability to be set to interrupt every 2ms and 0.5ms for
software ISRs.