Passport 2 NIBP Module (P/N 0670-00-0730 or 0670-00-0746-01) Theory of Operation
2 - 52 0070-10-0441 Passport 2®/Passport 2 LT™ Service Manual
To increase the reliability of the AT90S4433 device’s function as an over-pressure detector,
sleep mode will not be utilized. This prevents the possibility of the part becoming stuck in the
sleep state.
2.15.13 Memory
Flash Memory, U7
The program code will be stored in an Atmel AT49F4096A 4Mbit memory. The flash device
specified has the boot sector located at the bottom of the memory map at address 00000H
where the HC16Z1 expects to find the reset vectors.
Although the flash device requires additional power with CE* tied low, this prevents the need
for decoding logic where board real estate is limited.
Besides storing program code, other unprotected sectors of the flash memory may be used to
store less critical nonvolatile data if required. This would require dedicating an entire flash
sector for that purpose. However, due to small 8K byte parameter blocks in the flash, this is
not a gross waste of memory resources and prevents the need for an additional device.
Due to the fact that the flash reset input is held active low by the DS1811 until VCC is at a
valid level, inadvertent flash writes are avoided during power cycling and brown-outs. In
addition, the flash WE* signal defaults to the high state after reset and it is virtually
impossible for the flash write protocol to be reproduced due to random levels.
The HC16Z1 software can detect bad sector data in the flash by storing checksums which
can be verified during initialization.
2.15.14 CMOS Static RAM, U5
The SRAM is composed of one (U5) Samsung K6R1016C1C 64k-word x 16-bit part with two
separate chip select signals, CSRAMLB* and CSRAMHB*, connected to the LB* and UB*
pins respectively. The HC16Z1 R/W* signal is used to activate the SRAM WE* pins while
the OE* pin(s) are held low. The CS* signal is controlled by the UB* and LB* signals.
Although this much memory is unlikely to be needed during normal operation, it will help
when updating the flash in the field from the host. During this process, the HC16Z1 program
code must reside in the SRAM with additional room available for buffering data received
from the host.
2.15.15 CMOS EEPROM, U9
The HC16Z1 also has access to an Atmel AT25C020 2k-bit serial EEPROM through its QSPI
port. This EEPROM device will be used for storing an electronic serial number (ESN), NIBP
hardware version, and byte checksum. The ESN is a 32-bit long word, starting in memory
location 0. The hardware version information is one byte and follows immediately after the
ESN, in memory location 5. The checksum is also one byte, and follows immediately after the
hardware version info, in memory location 6. This information can be programmed via J7 or
off the board by removing the device from the socket.
This memory is hardware write protected by installing jumper J3 (JMODE*).
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