Passport 2®/Passport 2 LT™ Service Manual 0070-10-0441 2 - 15
Theory of Operation Front End Module
The processor is to be soldered to the board unprogrammed. Initial programming of the
bootloader is to be performed by the J204 BDM connector (Background Debug Mode). The
application code can also be installed by the BDM, or it can be downloaded via the module
bus once the bootloader is installed. Note that the BDM can also be used to facilitate board
testing, besides downloading code.
The RAM requirements are met by the internal SRAM array. The vector table lies within the
RAM. This allows the bootloader and application code to each install its own vectors at
runtime. Note that when a Flash module (in this case the bootloader module) is configured as
bootable, the initial PC, stack pointer, etc., are fetched from the module's shadow registers,
not the usual vector table. Therefore, the system is able to boot despite having undefined
RAM contents in the vector table at startup. One of the first tasks of the code is then to install
a valid vector table in the SRAM. This must be done before any exception processing can
occur.
2.2.7 I/O Ports and Software Register Programming
The interfaces to the processor are through the general purpose I/O ports, the QSPI, the SCI
(UART), and the timer ports. The internal ADC is also used for status monitoring.
General purpose I/O expansion is available principally on ports TA[2], TB[2:1], NQ,
SD[5:3], TD, TC[1:0], QS[6:4], QA[4].
Ports EL, EH, and AS[5:2] are used for microprocessor control signals and are configured as
outputs, except for Port EH bit 1, which is an input. The table below shows the bit
assignments for the ports. Port SD[2:0] is used for the SpO
2
ID bits and is listed below. Ports
TA and TB are used for the general purpose timer signals and are listed below. Port QS is
used for the QSPI signals and is listed below. Ports UA, TC, and AS are used for the SCI
signals and are listed below. Port DD is used for the BDM signals, but is not listed below.
Several ports are reserved for future interfaces using external address and data bus lines.
These ports are A, B, C, D, E, F, G, H, and J. All of the unused I/O are all configured as
outputs to eliminate the need to terminate these pins to a valid logic level.
ADC inputs and general purpose I/O are provided by Port QA and QB. The ports can be
used for all the ADC signals, but have multiple functions. They can be configured with
external analog multiplexer chips to accept as many as 18 analog inputs, utilizing the
multiplexed signals MA1 and MA0 on port QA bits 1 and 0. This is used to extend the
capabilities of the internal ADC. In this design, we accept 7 ADC inputs and don't need an
external analog multiplexer chip.
The function and pin assignments of these ports are described in the tables below. The exact
function of each signal will be more fully described in the discussion of the individual signal
processing circuits. Each pin can be individually configured as an input or output. Software
performs this configuration during initialization, and no subsequent changes are made
during operation.
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