Eaton EDR-5000 - Page 444

EDR-5000 IM02602007E
Synchronization inputs
Parameter Description
-.- No assignment
Sync-check.In-Sync Allowed Signal: In-Sync Allowed
DI-8P X1.DI 1 Signal: Digital Input
DI-8P X1.DI 2 Signal: Digital Input
DI-8P X1.DI 3 Signal: Digital Input
DI-8P X1.DI 4 Signal: Digital Input
DI-8P X1.DI 5 Signal: Digital Input
DI-8P X1.DI 6 Signal: Digital Input
DI-8P X1.DI 7 Signal: Digital Input
DI-8P X1.DI 8 Signal: Digital Input
DI-8 X6.DI 1 Signal: Digital Input
DI-8 X6.DI 2 Signal: Digital Input
DI-8 X6.DI 3 Signal: Digital Input
DI-8 X6.DI 4 Signal: Digital Input
DI-8 X6.DI 5 Signal: Digital Input
DI-8 X6.DI 6 Signal: Digital Input
DI-8 X6.DI 7 Signal: Digital Input
DI-8 X6.DI 8 Signal: Digital Input
Logic.LE1.Gate Out Signal: Output of the logic gate
Logic.LE1.Timer Out Signal: Timer Output
Logic.LE1.Out Signal: Latched Output (Q)
Logic.LE1.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE2.Gate Out Signal: Output of the logic gate
Logic.LE2.Timer Out Signal: Timer Output
Logic.LE2.Out Signal: Latched Output (Q)
Logic.LE2.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE3.Gate Out Signal: Output of the logic gate
Logic.LE3.Timer Out Signal: Timer Output
Logic.LE3.Out Signal: Latched Output (Q)
Logic.LE3.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE4.Gate Out Signal: Output of the logic gate
Logic.LE4.Timer Out Signal: Timer Output
Logic.LE4.Out Signal: Latched Output (Q)
Logic.LE4.Out inverted Signal: Negated Latched Output (Q NOT)
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