Eaton EDR-5000 - Page 658

EDR-5000 IM02602007E
Name Description
Logic.LE32.Out Signal: Latched Output (Q)
Logic.LE32.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE33.Gate Out Signal: Output of the logic gate
Logic.LE33.Timer Out Signal: Timer Output
Logic.LE33.Out Signal: Latched Output (Q)
Logic.LE33.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE34.Gate Out Signal: Output of the logic gate
Logic.LE34.Timer Out Signal: Timer Output
Logic.LE34.Out Signal: Latched Output (Q)
Logic.LE34.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE35.Gate Out Signal: Output of the logic gate
Logic.LE35.Timer Out Signal: Timer Output
Logic.LE35.Out Signal: Latched Output (Q)
Logic.LE35.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE36.Gate Out Signal: Output of the logic gate
Logic.LE36.Timer Out Signal: Timer Output
Logic.LE36.Out Signal: Latched Output (Q)
Logic.LE36.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE37.Gate Out Signal: Output of the logic gate
Logic.LE37.Timer Out Signal: Timer Output
Logic.LE37.Out Signal: Latched Output (Q)
Logic.LE37.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE38.Gate Out Signal: Output of the logic gate
Logic.LE38.Timer Out Signal: Timer Output
Logic.LE38.Out Signal: Latched Output (Q)
Logic.LE38.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE39.Gate Out Signal: Output of the logic gate
Logic.LE39.Timer Out Signal: Timer Output
Logic.LE39.Out Signal: Latched Output (Q)
Logic.LE39.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE40.Gate Out Signal: Output of the logic gate
Logic.LE40.Timer Out Signal: Timer Output
Logic.LE40.Out Signal: Latched Output (Q)
Logic.LE40.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE41.Gate Out Signal: Output of the logic gate
Logic.LE41.Timer Out Signal: Timer Output
Logic.LE41.Out Signal: Latched Output (Q)
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