Eaton EDR-5000 - Page 747

EDR-5000 IM02602007E
Release logic
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Ina ctiv e
Ac tive
V Ext Release PCC
81U-Under (50,05 Hz)
81O-Over (47,5 Hz)
V Internal R elease
V Ex t R elease PC C
Reclosure Release Cond
&
AND
&
AND
&
AND
>1
OR
&
AND
Dec oupling 1 Dec oupling 3 Dec oupling 2
ReclosureTrigger
Dec oupling 4 Dec oupling 5 Dec oupling 6
>1
OR
&
AND
f
2
V Ext Releas e PCC
Digital Input
0
Delay Timer
t-Release B lo
Inactive
Activ e
PCC Fuse Fail VT
&
AND
PCC Fuse F ail VT Digital Input
&
AND
VLL< Releas e
&
AND
VAB VBC VCA
VLL> Releas e
&
AND
VAB VBC VCA
&
AND
>1
OR
ReCon
Mains decoupling
Voltage Release Frequency Release
Mains settle timer (each High-Signal at the input will
restart die fall back delay timer)
V<
V> 81U-Under
81O-Ov er
Q->&V <.Decoupling Distributed Gener ator
DI.x
&
AND
ReCon .Release
ReCon.reconnec ted
1
Distributed Energy Resource already mains
parallel: true/false
Voltage Transformer Supervision