GE Multilin F60 Feeder Protection System 5-199
5 SETTINGS 5.6 GROUPED ELEMENTS
5
The differential current is produced as an unbalance current between the ground current of the neutral CT (IG) and the neu-
tral current derived from the phase CTs (IN = IA + IB + IC):
(EQ 5.21)
The relay automatically matches the CT ratios between the phase and ground CTs by re-scaling the ground CT to the
phase CT level. The restraining signal ensures stability of protection during CT saturation conditions and is produced as a
maximum value between three components related to zero, negative, and positive-sequence currents of the three phase
CTs as follows:
(EQ 5.22)
The zero-sequence component of the restraining signal (IR0) is meant to provide maximum restraint during external ground
faults, and therefore is calculated as a vectorial difference of the ground and neutral currents:
(EQ 5.23)
The equation above brings an advantage of generating the restraining signal of twice the external ground fault current,
while reducing the restraint below the internal ground fault current. The negative-sequence component of the restraining
signal (IR2) is meant to provide maximum restraint during external phase-to-phase faults and is calculated as follows:
(EQ 5.24)
Following complete de-energization of the windings (all three phase currents below 5% of nominal for at least five cycles),
the relay uses a multiplier of 1 in preparation for the next energization. The multiplier of 3 is used during normal operation;
that is, two cycles after the winding has been energized. The lower multiplier is used to ensure better sensitivity when ener-
gizing a faulty winding.
The positive-sequence component of the restraining signal (IR1) is meant to provide restraint during symmetrical condi-
tions, either symmetrical faults or load, and is calculated according to the following algorithm:
1 If of phase CT, then
2 If , then
3else
4else
Under load-level currents (below 150% of nominal), the positive-sequence restraint is set to 1/8th of the positive-sequence
current (line 4). This is to ensure maximum sensitivity during low-current faults under full load conditions. Under fault-level
currents (above 150% of nominal), the positive-sequence restraint is removed if the zero-sequence component is greater
than the positive-sequence (line 3), or set at the net difference of the two (line 2).
The raw restraining signal (Irest) is further post-filtered for better performance during external faults with heavy CT satura-
tion and for better switch-off transient control:
(EQ 5.25)
where k represents a present sample, k – 1 represents the previous sample, and α is a factory constant (α<1). The equa-
tion above introduces a decaying memory to the restraining signal. Should the raw restraining signal (Irest) disappear or
drop significantly, such as when an external fault gets cleared or a CT saturates heavily, the actual restraining signal (Igr(k))
will not reduce instantly but will keep decaying decreasing its value by 50% each 15.5 power system cycles.
Having the differential and restraining signals developed, the element applies a single slope differential characteristic with a
minimum pickup as shown in the logic diagram below.
Igd IG IN+ IG IA IB IC+++==
Irest max IR0 IR1 IR2,,()=
IR0 IG IN– IG IA IB IC++()–==
Igr k() max Irest k()α Igr k 1–()×,()=
To Next Page
Loading...
