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Harris APEX - FLO FPGA, SFN FIFO Status, Screen 4;5

Harris APEX
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APEX Exciter Incorporating FLO Technology
Details of the Exciter Status Screens Navigating the LCD Display Screens
2604s300.fm
03/08/07 888-2604-001 Page: 3-17
WARNING: Disconnect primary power prior to servicing.
3.4.4.6 FLO FPGA, SFN FIFO Status, Screen 4/5
FPGA Status4.bmp
Figure 3-15 FLO FPGA, FSN FIFO Status, Screen 4/5
The parameters of the SFN FIFO Status screen are as follows.
Core Stall: YES (in red) indicates error, NO (in black) indicated OK
Overflow: YES (in red) indicates error, NO (in black) indicated OK
Underflow: YES (in red) indicates error, NO (in black) indicated OK
Too Full: YES (in red) indicates error, NO (in black) indicated OK
Too Low: YES (in red) indicates error, NO (in black) indicated OK
Seq Err: YES (in red) indicates error, NO (in black) indicated OK
Parity Err: YES (in red) indicates error, NO (in black) indicated OK
FIFO Level%: Decimal percentage

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