Harris DA-DHR6804+D - Da-Dh6804+D

Chapter 1
Introduction
4
Copyright © 2010, Harris Corporation
 Selectable input EQ bypass
 Reclockable for 270 Mb/s, 1.485 Gb/s, or 2.97 Gb/s SMPTE and DVB-ASI
signals
 Three selectable reclocking modes (automatic, manual, enforce bypass)
 Automatic bypassing reclock stage if not relockable
 Reclock status and data rate report
 Automatic slew rate control for output signal
 Automatic power saving if no input signal or no termination on the output
BNC
 Local and remote control
 Module hot swappable
DA-DH6804+D
The main features for the DA-DH6804+D are listed below. Figure 1-2 shows a
basic signal flow diagram for this distribution amplifier module.
Figure 1-2 DA-DH6804+D Signal Flow Diagram
 Operates with standard dual slot distribution amplifier back module (see
page 14)
 Passes signals at data rates from 5 Mb/s to 3 Gb/s
 Four selectable channel configurations:
 1×8_ACO: 1 input to 8 outputs with auto changeover
The signal on SDI In_1 is distributed to 8 outputs. If the signal at SDI In_1
disappears, the distribution amplifier outputs are switched to SDI In_2 (if a
signal at SDI In_2 is detected).
When the signal reappears SDI In_1, the outputs are switched back to SDI
In_1 from SDI In_2 automatically.
 1×8_ In_1: SDI In_1 to 8 outputs
 1×8_ In_2: SDI In_2 to 8 outputs