Harris DA-DHR6804+D - Page 20

Chapter 1
Introduction
6
Copyright © 2010, Harris Corporation
 1×8_ In_2: SDI In_2 to 8 outputs
 2_1×4: 2 independent 1×4
 SDI In_1 to SDI Out_1, 1-4
 SDI In_2 to SDI Out_2, 1-4
 Input signal presence detect and report
 Automatic input cable equalization
 Selectable +6 dB gain to use external passive 75 2×1 splitter (via CCS only)
 Selectable input EQ bypass
 Reclockable for 270 Mb/s SMPTE and DVB-ASI signals
 Three selectable reclocking modes (automatic, manual, enforce bypass)
 Automatic bypassing reclock stage if not relockable
 Reclock status and data rate report
 Automatic slew rate control for output signal
 Automatic power saving if not input signal or no termination on the output
BNC
 Local and remote control
 Module hot swappable