Hitachi EH-150 Series - Detail of Output Register

Chapter 5 Control of EH-SIO
5 - 12
5.2.3 Detail of output register
 Configuration of control register
The control register consists of 16 bits. A meaning is different for each bit.
WY r u s 4
Bit
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
Abbreviation
YCNT1
YHS1
YCV1
--
PRST1
--
RS1
ER1
System area
WY r u s 5
Bit
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
Abbreviation
YCNT2
YHS2
YCV2
--
PRST2
--
RS2
ER2
System area
Figure 5.11 Configuration of control register
Table 5.4 Contents of control register
Bit
Abbreviation
Name
Contents of each flag
79
YCNT1
Y-CoNTinue flag
It is set to "1" when there is a continuation of the data sent to EH-SIO (port 1)
from CPU.
78
YHS1
Y-HandShake flag
It is set to "1" when sending data to EH-SIO (port 1) from CPU.
77
YCV1
Y-Command Valid flag
It is set to "1" when the command to a port 1 is decided.
76
--
Used by system.
75
PRST1
Port1 ReSeT
Please set 1, when you return the state of a port 1 to the state at the time of a
power supply ON (before initial setting completion). It resets by the system.
74
--
Undefined.
73
RS1*
port1 RS signal control
RS signal of a port 1 is controllable at the time of free protocol mode / modem
control enable. RS signal will be set to High if 1 is set.
72
ER1*
port1 ER signal control
ER signal of a port 1 is controllable at the time of free protocol mode / modem
control enable. ER signal will be set to High if 1 is set.
71 to 64
--
System Area
Used by system.
Bit
Abbreviation
Name
Contents of each flag
95
YCNT2
Y-CoNTinue flag
It is set to "1" when there is a continuation of the data sent to EH-SIO (port 2)
from CPU.
94
YHS2
Y-HandShake flag
It is set to "1" when sending data to EH-SIO (port 2) from CPU.
93
YCV2
Y-Command Valid flag
It is set to "1" when the command to a port 2 is decided.
92
--
Used by system.
91
PRST2
Port2 ReSeT
Please set 1, when you return the state of a port 2 to the state at the time of a
power supply ON (before initial setting completion). It resets by the system.
90
--
Undefined.
89
RS2*
port2 RS signal control
RS signal of a port 2 is controllable at the time of free protocol mode / modem
control enable. RS signal will be set to High if 1 is set.
88
ER2*
port2 ER signal control
ER signal of a port 2 is controllable at the time of free protocol mode / modem
control enable. ER signal will be set to High if 1 is set.
87 to 80
--
System Area
Used by system
* The bit does not work when control signal setting is invalid or this bit is set to 1 before initial setting is completed. Moreover,
when communication I/F of the port 1 or 2 is RS-422 /485, this bit is not used.
« Note »
 Only "PRST", "RS", and "ER" of a control register can be operated by user.
The other bits and other system area (WYus6 and WYus7) are used by the system, please do not write those area,
otherwise EH-SIO does not work properly.
 When EH-SIO has stopped by serious failure, reset by the PRST flag cannot be performed.
 When EH-SIO is reset with a PRST flag, please initialize EH-SIO (an initialization request flag is turned on) by
TRNS 9 command.