Rev. 1.71 72 April 11, 2017 Rev. 1.71 73 April 11, 2017
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
IntheCompareMatchOutputMode,theST0IO1~ST0IO0bitsdeterminehowtheTMoutputpin
changesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbe
setuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfrom
theComparatorA.WhentheST0IO1~ST0IO0 bitsarebothzero,thennochangewilltakeplace
ontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingtheST0OCbit.Note
thattheoutputlevelrequestedbytheST0IO1~ST0IO0bitsmustbedifferentfromtheinitial
valuesetupusingtheST0OCbitotherwisenochangewilloccurontheTMoutputpinwhena
comparematchoccurs.AftertheTMoutputpinchangesstateitcanberesettoitsinitiallevelby
changingtheleveloftheST0ONbitfromlowtohigh.
InthePWMMode,theST0IO1andST0IO0bitsdeterminehowtheTMoutputpinchanges
statewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodiedby
changingthesetwobits.ItisnecessarytochangethevaluesoftheST0IO1andST0IO0bitsonly
aftertheTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccuriftheST0IO1and
ST0IO0bitsarechangedwhentheTMisrunning.
bit
3 ST0OC:STM0Outputcontrolbit
CompareMatchOutputMode
0:Initiallow
1:Initialhigh
PWMoutputMode/SinglePulseOutputMode
0:Activelow
1:Activehigh
ThisistheoutputcontrolbitfortheSTMoutputpin.ItsoperationdependsuponwhetherSTM
isbeingusedintheCompareMatchOutputModeorinthePWMoutputMode/SinglePulse
OutputMode.IthasnoeffectiftheSTMisintheTimer/CounterMode.IntheCompareMatch
OutputModeitdeterminesthelogicleveloftheSTMoutputpinbeforeacomparematchoccurs.
InthePWMoutputModeitdeterminesifthePWMsignalisactivehighoractivelow.Inthe
SinglePulseOutputModeitdeterminesthelogicleveloftheSTMoutputpinwhentheST0ON
bitchangesfromlowtohigh.
bit
2 ST0POL:STM0OutputpolarityControl
0:Non-invert
1:Invert
ThisbitcontrolsthepolarityoftheSTM0outputpin.WhenthebitissethightheSTMoutputpin
willbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheSTMisintheTimer/
CounterMode.
bit1 ST0DPX:STM0PWMperiod/dutyControl
0:CCRP-period;CCRA-duty
1:CCRP-duty;CCRA-period
Thisbit,determineswhichoftheCCRAandCCRPregistersareusedforperiodanddutycontrol
ofthePWMwaveform.
bit0 ST0CCLR:SelectSTM0Counterclearcondition
0:STM0ComparatorPmatch
1:STM0ComparatorAmatch
Thisbitisusedtoselectthemethodwhichclearsthecounter.RememberthattheStandardSTM
containstwocomparators,ComparatorAandComparatorP,either ofwhichcanbeselectedto
cleartheinternalcounter.WiththeST0CCLRbitsethigh,thecounterwillbeclearedwhena
comparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbecleared
whenacomparematchoccursfromtheComparator Porwithacounteroverflow.Acounter
overowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.The
ST0CCLRbitisnotusedinthePWMoutputmode,SinglePulseorInputCaptureMode.