Rev. 1.50 158 August 28, 2017 Rev. 1.50 159 August 28, 2017
HT66F0175/HT66F0185
A/D Flash MCU with EEPROM
HT66F0175/HT66F0185
A/D Flash MCU with EEPROM
Bit4 OERR:Overrunerrorag
0:Nooverrunerrorisdetected
1:Overrunerrorisdetected
TheOERRagistheoverrunerroragwhichindicateswhenthereceiverbufferhas
overowed.Whenthisreadonlyagis“0”,itindicatesthatthereisnooverrunerror.
Whentheagis“1”,itindicatesthatanoverrunerroroccurswhichwillinhibitfurther
transferstotheRXRreceivedataregister.Theagisclearedbyasoftwaresequence,
whichisareadtothestatusregisterUSRfollowedbyanaccesstotheRXRdata
register.
Bit3 RIDLE:Receiverstatus
0:Datareceptionisinprogress(databeingreceived)
1:Nodatareceptionisinprogress(receiverisidle)
TheRIDLEagisthereceiverstatusag.Whenthisreadonlyagis“0”,itindicates
thatthereceiverisbetweentheinitialdetectionofthestartbitandthecompletionof
thestopbit.Whentheagis“1”,itindicatesthatthereceiverisidle.Betweenthe
completionofthestopbitandthedetectionofthenextstartbit,theRIDLEbitis“1”
indicatingthattheUARTreceiverisidleandtheRXpinstaysinlogichighcondition.
Bit2 RXIF:ReceiveRXRdataregisterstatus
0:RXRdataregisterisempty
1:RXRdataregisterhasavailabledata
TheRXIFagisthereceivedataregisterstatusag.Whenthisreadonlyagis“0”,
itindicatesthattheRXRreaddataregisterisempty.Whentheagis“1”,itindicates
thattheRXRreaddataregistercontainsnewdata.Whenthecontentsoftheshift
registeraretransferredtotheRXRregister,aninterruptisgeneratedifRIE=1inthe
UCR2register.Ifoneormoreerrorsaredetectedinthereceivedword,theappropriate
receive-relatedagsNF,FERR,and/orPERRaresetwithinthesameclockcycle.The
RXIFagisclearedwhentheUSRregisterisreadwithRXIFset,followedbyaread
fromtheRXRregister,andiftheRXRregisterhasnodataavailable.
Bit1 TIDLE:Transmissionstatus
0:Datatransmissionisinprogress(databeingtransmitted)
1:Nodatatransmissionisinprogress(transmitterisidle)
TheTIDLEflagisknownasthetransmissioncompleteflag.Whenthisreadonly
agis“0”,itindicatesthatatransmissionisinprogress.Thisagwillbesetto“1”
whentheTXIFagis“1”andwhenthereisnotransmitdataorbreakcharacterbeing
transmitted.WhenTIDLEisequalto1,theTXpinbecomesidlewiththepinstate
inlogichighcondition.TheTIDLEagisclearedbyreadingtheUSRregisterwith
TIDLEsetandthenwritingtotheTXRregister.Theagisnotgeneratedwhenadata
characterorabreakisqueuedandreadytobesent.
Bit0 TXIF:TransmitTXRdataregisterstatus
0:Characterisnottransferredtothetransmitshiftregister
1:Characterhastransferredtothetransmitshiftregister(TXRdataregisterisempty)
TheTXIFagisthetransmitdataregisteremptyag.Whenthisreadonlyagis“0”,
itindicatesthatthecharacterisnottransferredtothetransmittershiftregister.When
theagis“1”,itindicatesthatthetransmittershiftregisterhasreceivedacharacter
fromtheTXRdataregister.TheTXIFflagisclearedbyreadingtheUARTstatus
register(USR)withTXIFsetandthenwritingtotheTXRdataregister.Notethat
whentheTXENbitisset,theTXIFagbitwillalsobesetsincethetransmitdata
registerisnotyetfull.