Rev. 1.50 24 August 28, 2017 Rev. 1.50 25 August 28, 2017
HT66F0175/HT66F0185
A/D Flash MCU with EEPROM
HT66F0175/HT66F0185
A/D Flash MCU with EEPROM
System Architecture
Akeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributed
totheirinternalsystemarchitecture.Therangeofdevicestakeadvantageoftheusualfeaturesfound
withinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance.
Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstruction
executionareoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withthe
exceptionofbranchorcallinstructions.An8-bitwideALUisusedinpracticallyallinstructionset
operations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,
branchdecisions,etc.TheinternaldatapathissimpliedbymovingdatathroughtheAccumulator
andtheALU.CertaininternalregistersareimplementedintheDataMemoryandcanbedirectly
orindirectlyaddressed.Thesimpleaddressingmethodsoftheseregistersalongwithadditional
architecturalfeaturesensurethataminimumofexternalcomponentsisrequiredtoprovidea
functionalI/OandA/Dcontrolsystemwithmaximumreliabilityandexibility.Thismakesthese
devicessuitableforlow-cost,high-volumeproductionforcontrollerapplications.
Clocking and Pipelining
Themainsystemclock,derivedfromeitheraHXT,LXT,HIRCorLIRCoscillatorissubdivided
intofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincremented
atthebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.Theremaining
T2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clock
cycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplace
inconsecutiveinstructioncycles,thepipeliningstructureofthemicrocontrollerensuresthat
instructionsareeffectivelyexecutedinoneinstructioncycle.Theexceptiontothisareinstructions
wherethecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhich
casetheinstructionwilltakeonemoreinstructioncycletoexecute.
System Clocking and Pipelining