Rev. 1.50 56 August 28, 2017 Rev. 1.50 57 August 28, 2017
HT66F0175/HT66F0185
A/D Flash MCU with EEPROM
HT66F0175/HT66F0185
A/D Flash MCU with EEPROM
Watchdog Timer Operation
TheWatchdogTimeroperatesbyprovidingadeviceresetwhenitstimeroverows.Thismeans
thatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallyclearthe
WatchdogTimerbeforeitoverowstopreventtheWatchdogTimerfromexecutingareset.Thisis
doneusingtheclearwatchdoginstruction.Iftheprogrammalfunctionsforwhateverreason,jumps
toanunknownlocation,orentersanendlessloop,theseclearinstructionswillnotbeexecutedinthe
correctmanner,inwhichcasetheWatchdogTimerwilloverowandresetthedevice.Withregardto
theWatchdogTimerenable/disablefunction,therearevebits,WE4~WE0,intheWDTCregister
tooffertheenable/disablecontrolandresetcontroloftheWatchdogTimer.TheWDTfunctionwill
bedisabledwhentheWE4~WE0bitsaresettoavalueof10101BwhiletheWDTfunctionwill
beenablediftheWE4~WE0bitsareequalto01010B.IftheWE4~WE0bitsaresettoanyother
values,except01010Band10101B,itwillresetthedeviceafter2~3f
LIRC
clockcycles.Afterpower
onthesebitswillhaveavalueof01010B.
WE4 ~ WE0 Bits WDT Function
10101B Disable
01010B Enable
Any other value Reset MCU
Watchdog Timer Enable/Disable Control
Undernormalprogramoperation,aWatchdogTimertime-outwillinitialiseadeviceresetandset
thestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimer
time-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStack
Pointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer.
TherstisaWDTreset,whichmeansacertainvalueexcept01010Band10101Bwrittenintothe
WE4~WE0eld,thesecondisusingtheWatchdogTimersoftwareclearinstructionandthethirdis
viaaHALTinstruction.
ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistouse
thesingle“CLRWDT”instructiontocleartheWDTcontents.
Themaximumtimeoutperiodiswhenthe2
18
divisionratioisselected.Asanexample,witha
32kHzLIRCoscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround8
secondforthe2
18
divisionratioandaminimumtimeoutof7.8msforthe2
8
divisionration.
CLR WDT”Instruction
8-stage Divider WDT Prescaler
WE4~WE0 bits
WDTC
Register
Reset MCU
f
SUB
f
SUB
/2
8
8-to-1 MUX
CLR
WS2~WS0
(f
SUB
/2
8
~ f
SUB
/2
18
)
WDT Time-out
(2
8
/f
SUB
~ 2
18
/f
SUB
)
“HALT”Instruction
Watchdog timer