Holtek HT66F0175 - U�RT Receiver

Rev. 1.50 164 August 28, 2017 Rev. 1.50 165 August 28, 2017
HT66F0175/HT66F0185
A/D Flash MCU with EEPROM
HT66F0175/HT66F0185
A/D Flash MCU with EEPROM
Thissequenceofeventscannowberepeatedtosendadditionaldata.Itshouldbenotedthatwhen
TXIF=0,datawillbeinhibitedfrombeingwrittentotheTXRregister.ClearingtheTXIFagis
alwaysachievedusingthefollowingsoftwaresequence:
1.AUSRregisteraccess
2.ATXRregisterwriteexecution
Theread-onlyTXIFagissetbytheUARThardwareandifsetindicatesthattheTXRregisteris
emptyandthatotherdatacannowbewrittenintotheTXRregisterwithoutoverwritingtheprevious
data.IftheTEIEbitisset,thentheTXIFagwillgenerateaninterrupt.Duringadatatransmission,
awriteinstructiontotheTXRregisterwillplacethedataintotheTXRregister,whichwillbe
copiedtotheshiftregisterattheendofthepresenttransmission.Whenthereisnodatatransmission
inprogress,awriteinstructiontotheTXRregisterwillplacethedatadirectlyintotheshiftregister,
resultinginthecommencementofdatatransmission,andtheTXIFbitbeingimmediatelyset.When
aframetransmissioniscomplete,whichhappensafterstopbitsaresentorafterthebreakframe,the
TIDLEbitwillbeset.TocleartheTIDLEbitthefollowingsoftwaresequenceisused:
1.AUSRregisteraccess
2.ATXRregisterwriteexecution
NotethatboththeTXIFandTIDLEbitsareclearedbythesamesoftwaresequence.
Transmitting Break
IftheTXBRKbitisset,thenthebreakcharacterswillbesentonthenexttransmission.Break
charactertransmissionconsistsofastartbit,followedby13xN“0”bits,whereN=1,2,etc.Ifa
breakcharacteristobetransmitted,thentheTXBRKbitmustberstsetbytheapplicationprogram
andthenclearedtogeneratethestopbits.Transmittingabreakcharacterwillnotgenerateatransmit
interrupt.Notethatabreakconditionlengthisatleast13bitslong.IftheTXBRKbitiscontinually
keptatalogichighlevel,thenthetransmittercircuitrywilltransmitcontinuousbreakcharacters.
AftertheapplicationprogramhasclearedtheTXBRKbit,thetransmitterwillnishtransmittingthe
lastbreakcharacterandsubsequentlysendoutoneortwostopbits.Theautomaticlogichighatthe
endofthelastbreakcharacterwillensurethatthestartbitofthenextframeisrecognized.
UART Receiver
TheUARTiscapableofreceivingwordlengthsofeither8or9bitscanbeselectedbyprogramming
theBNObitintheUCR1register.WhenBNObitisset,thewordlengthwillbesetto9bits.In
thiscasethe9
th
bit,whichistheMSB,willbestoredintheRX8bitintheUCR1register.Atthe
receivercoreliestheReceiverShiftRegistermorecommonlyknownastheRSR.Thedatawhich
isreceivedontheRXexternalinputpinissenttothedatarecoveryblock.Thedatarecoveryblock
operatingspeedis16timesthatofthebaudrate,whilethemainreceiveserialshifteroperatesatthe
baudrate.AftertheRXpinissampledforthestopbit,thereceiveddatainRSRistransferredtothe
receivedataregister,iftheregisterisempty.ThedatawhichisreceivedontheexternalRXinputpin
issampledthreetimesbyamajoritydetectcircuittodeterminethelogiclevelthathasbeenplaced
ontotheRXpin.ItshouldbenotedthattheRSRregister,unlikemanyotherregisters,isnotdirectly
mappedintotheDataMemoryareaandassuchisnotavailabletotheapplicationprogramfordirect
read/writeoperations.
Receiving Data
WhentheUARTreceiverisreceivingdata,thedataisseriallyshiftedinontheexternalRXinput
pintotheshiftregister,withtheleastsignicantbitLSBrst.TheRXRregisterisatwobytedeep
FIFOdatabuffer,wheretwobytescanbeheldintheFIFOwhilethe3
rd
bytecancontinuetobe
received.NotethattheapplicationprogrammustensurethatthedataisreadfromRXRbeforethe