Holtek HT66F0175 - Page 166

Rev. 1.50 166 August 28, 2017 Rev. 1.50 167 August 28, 2017
HT66F0175/HT66F0185
A/D Flash MCU with EEPROM
HT66F0175/HT66F0185
A/D Flash MCU with EEPROM
3
rd
bytehasbeencompletelyshiftedin,otherwisethe3
rd
bytewillbediscardedandanoverrunerror
OERRwillbesubsequentlyindicated.Thestepstoinitiateadatatransfercanbesummarizedas
follows:
• MakethecorrectselectionoftheBNO,PRT,PRENandSTOPSbitstodenetherequiredword
length,paritytypeandnumberofstopbits.
• SetuptheBRGregistertoselectthedesiredbaudrate.
• SettheRXENbittoensurethattheUARTreceiverisenabledandtheRXpinisusedasaUART
receiverpin.
Atthispointthereceiverwillbeenabledwhichwillbegintolookforastartbit.
Whenacharacterisreceived,thefollowingsequenceofeventswilloccur:
• TheRXIFbitintheUSRregisterwillbesetthenRXRregisterhasdataavailable,atleastone
morecharactercanberead.
• WhenthecontentsoftheshiftregisterhavebeentransferredtotheRXRregisterandiftheRIE
bitisset,thenaninterruptwillbegenerated.
• Ifduringreception,aframeerror,noiseerror,parityerrororanoverrunerrorhasbeendetected,
thentheerroragscanbeset.
TheRXIFbitcanbeclearedusingthefollowingsoftwaresequence:
1.AUSRregisteraccess
2.ARXRregisterreadexecution
Receiving Break
AnybreakcharacterreceivedbytheUARTwillbemanagedasaframingerror.Thereceiverwill
countandexpectacertainnumberofbittimesasspeciedbythevaluesprogrammedintotheBNO
andSTOPSbits.Ifthebreakismuchlongerthan13bittimes,thereceptionwillbeconsideredas
completeafterthenumberofbittimesspeciedbyBNOandSTOPS.TheRXIFbitisset,FERR
isset,zerosareloadedintothereceivedataregister,interruptsaregeneratedifappropriateandthe
RIDLEbitisset.Ifalongbreaksignalhasbeendetectedandthereceiverhasreceivedastartbit,
thedatabitsandtheinvalidstopbit,whichsetstheFERRag,thereceivermustwaitforavalid
stopbitbeforelookingforthenextstartbit.Thereceiverwillnotmaketheassumptionthatthe
breakconditiononthelineisthenextstartbit.Abreakisregardedasacharacterthatcontainsonly
zeroswiththeFERRagset.Thebreakcharacterwillbeloadedintothebufferandnofurtherdata
willbereceiveduntilstopbitsarereceived.ItshouldbenotedthattheRIDLEreadonlyagwillgo
highwhenthestopbitshavenotyetbeenreceived.ThereceptionofabreakcharacterontheUART
registerswillresultinthefollowing:
• Theframingerrorag,FERR,willbeset.
• Thereceivedataregister,RXR,willbecleared.
• TheOERR,NF,PERR,RIDLEorRXIFagswillpossiblybeset.
Idle Status
Whenthereceiverisreadingdata,whichmeansitwillbeinbetweenthedetectionofastartbitand
thereadingofastopbit,thereceiverstatusagintheUSRregister,otherwiseknownastheRIDLE
ag,willhaveazerovalue.Inbetweenthereceptionofastopbitandthedetectionofthenextstart
bit,theRIDLEagwillhaveahighvalue,whichindicatesthereceiverisinanidlecondition.