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Rev. 1.50 198 August 28, 2017 Rev. 1.50 199 August 28, 2017
HT66F0175/HT66F0185
A/D Flash MCU with EEPROM
HT66F0175/HT66F0185
A/D Flash MCU with EEPROM
SUBM A,[m]
SubtractDataMemoryfromACCwithresultinDataMemory
Description ThespeciedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis
storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCagwillbe
clearedto0,otherwiseiftheresultispositiveorzero,theCagwillbesetto1.
Operation [m]←ACC−[m]
Affectedag(s) OV,Z,AC,C
SUB A,x
SubtractimmediatedatafromACC
Description TheimmediatedataspeciedbythecodeissubtractedfromthecontentsoftheAccumulator.
TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC
agwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCagwillbesetto1.
Operation ACC←ACC−x
Affectedag(s) OV,Z,AC,C
SWAP [m]
SwapnibblesofDataMemory
Description Thelow-orderandhigh-ordernibblesofthespeciedDataMemoryareinterchanged.
Operation [m].3~[m].0↔[m].7~[m].4
Affectedag(s) None
SWAPA [m]
SwapnibblesofDataMemorywithresultinACC
Description Thelow-orderandhigh-ordernibblesofthespeciedDataMemoryareinterchanged.The
resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.
Operation ACC.3~ACC.0←[m].7~[m].4
ACC.7~ACC.4←[m].3~[m].0
Affectedag(s) None
SZ [m]
SkipifDataMemoryis0
Description IfthecontentsofthespeciedDataMemoryis0,thefollowinginstructionisskipped.Asthis
requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo
cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.
Operation Skipif[m]=0
Affectedag(s) None
SZA [m]
SkipifDataMemoryis0withdatamovementtoACC
Description ThecontentsofthespeciedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero,
thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction
whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the
programproceedswiththefollowinginstruction.
Operation ACC←[m]
Skipif[m]=0
Affectedag(s) None
SZ [m].i
SkipifbitiofDataMemoryis0
Description IfbitiofthespeciedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires
theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle
instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.
Operation Skipif[m].i=0
Affectedag(s) None

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