Rev. 1.50 94 August 28, 2017 Rev. 1.50 95 August 28, 2017
HT66F0175/HT66F0185
A/D Flash MCU with EEPROM
HT66F0175/HT66F0185
A/D Flash MCU with EEPROM
Timer/Counter Mode
Toselectthismode,bitsTnM1andTnM0intheTMnC1registershouldbesetto11respectively.
TheTimer/CounterModeoperatesinanidenticalwaytotheCompareMatchOutputMode
generatingthesameinterruptags.TheexceptionisthatintheTimer/CounterModetheTMnoutput
pinisnotused.ThereforetheabovedescriptionandTimingDiagramsfortheCompareMatch
OutputModecanbeusedtounderstanditsfunction.AstheTMnoutputpinisnotusedinthismode,
thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.
PWM Output Mode
Toselectthismode,bitsTnM1andTnM0intheTMnC1registershouldbesetto10respectively
andalsotheTnIO1andTnIO0bitsshouldbesetto10respectively.ThePWMfunctionwithin
theTMnisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol,
illuminationcontroletc.Byprovidingasignalofxedfrequencybutofvaryingdutycycleonthe
TMnoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMS
values.
AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgenerated
waveformisextremelyflexible.InthePWMmode,theTnCCLRbithasnoeffectasthePWM
period.BothoftheCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregister
isusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheother
oneisusedtocontrolthedutycycle.Whichregisterisusedtocontroleitherfrequencyordutycycle
isdeterminedusingtheTnDPXbitintheTMnC1register.ThePWMwaveformfrequencyandduty
cyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.
Aninterruptag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematch
occursfromeitherComparatorAorComparatorP.TheTnOCbitintheTMnC1registerisusedto
selecttherequiredpolarityofthePWMwaveformwhilethetwoTnIO1andTnIO0bitsareusedto
enablethePWMoutputortoforcetheTMnoutputpintoaxedhighorlowlevel.TheTnPOLbit
isusedtoreversethepolarityofthePWMoutputwaveform.
• 16-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=0
CCRP 1~255 0
Period CCRP
×
256 65536
Duty CCRA
Iff
SYS
=16MHz,TMnclocksourceisf
SYS
/4,CCRP=2andCCRA=128,
TheTMnPWMoutputfrequency=(f
SYS
/4)/(2×256)=f
SYS
/2048=7.8125kHz,duty=128/(2×256)=
25%.
IftheDutyvaluedenedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthe
PWMoutputdutyis100%.
• 16-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=1
CCRP 1~255 0
Period CCRA
Duty CCRP
×
256 65536
ThePWMoutputperiodisdeterminedbytheCCRAregistervaluetogetherwiththeTMclockwhile
thePWMdutycycleisdenedbythe(CCRP×256)valueexceptwhentheCCRPvalueisequalto0.