DIO
and
DIO II are
both
asynchronous busses, with DIO II being a superset of DIO.
The
timing
of
DIO II has been changed from
that
of DIO.
The
master initiates a bus cycle by asserting
the
address
and
the
appropriate
address strobe(
s)
and
data
strobe( s).
The
slave
then
responds
by taking
the
data
off
the
bus during a
WRITE
cycle or by
putting
data
on
the
bus during
a READ cycle.
The
slave
then
completes
the
cycle by asserting one of
the
DTACK*
(Data
Transfer ACKnowledge) signals.
In
DIO-II
there
are four distinct types of bus cycles:
• Address only.
• Single
data
transfer.
• Block
data
transfer.
• Read modify write (RMW).
DIO upgrades are available for
the
computer
and
expander
to
convert DIO-II system slots
to
2·-
or
4-s10t8
for use with
standard
DIO accessory cards.
The
earlier
HP
98256A 256 Kbyte
and
HP
98257 1 Mbyte RAM cards are not
supported
in this configuration, due
to
bus timing
and
addressing differences.
Functional Description
85
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