Translation Tables
\Vhen
the
CPU
attempts
an
access
to
a logical address whose
translation
is
not
resident in
the
TLB,
an
address
translation
cycle
must
be
executed.
This
is called a
table
walk.
The
table
algorithms used for address
translation
use segnlent
and
page tables,
and
user/supervisor
root
pointers.
Two levels
of
tables exist.
The
second layer is
the
Page
table, which contains
the
physical
addresses, called translations.
The
first layer is
the
Segment table, which mainly contains
addresses of page tables. 32-bit logical address
are
divided into
three
offsets.
Separate
tables
can exist for user
and
supervisor accesses.
Root pointers are
hardware
registers
that
contain
the
upper
20
bits
of
the
starting
address of
the
segment table. One
pointer
is used for supervisor mode,
and
one for user.
The
segment
table
offset is
concatenated
with
selected root pointer,
creating
the
address of
the
segment
table
entry.
The
MMU performs a memory cycle
and
reads from
that
address.
Page
table
offset is
concatenated
to
the
bottom
of
the
data
from
the
segment table, which
create
the
address of
the
page
table
entry.
The
MMU reads
this
address from memory. Information
returned
is
the
address of
the
physical page.
This
is
the
translation,
and
it
is
stored in
the
TLB
for
future
reference.
Translation Lookaside Buffer
The
TLB
is
a cache for address translations. When a
translation
has
been completed,
it
is
stored in
the
TLB
so
that
a complete
translation
doesn't
always need
to
be
done when
that
logical address is accessed again.
The
organization of
the
TLB
is a direct
mapped
set associative
cache.
The
depth
of
the
TLB
is 2K entries,
with
1K for user
and
1K for supervisor.
Because
the
TLB
stores
data
from main memory, any changes in
the
translation
tables
must
be
followed
with
either
a complete
or
selective purge of
the
TLB.
The
TLB
must
also
be
purged
whenever
the
root pointers
are
changed.
The
Model 350 processor
board
automatically purges
the
entire
TLB
whenever
either
of
the
root pointers
are
written.
Cache
On
the
processor, a 32
Kbyte
virtual
cache is used for
data
and
instructions.
It
is
a
static
lnemory
array
that
is fast enough
to
allow
the
CPU
to
read
data
in
three
clock states,
or
120
ns.
This
cache
is
set-associative
with
a set size of one.
When
data
is coming into
the
cache,
there
is exactly one place where
it
can
be
stored. Cache
is
organized as 2048 lines of
16
bytes
each. Hit
rate
of this cache is
about
79% because
of
this
larger line size.
Two
banks
of RAMs
are
used.
The
larger group is
the
cache
data
RAMs, where
the
actual
data
is stored. A smaller group is
the
cache key, where
the
upper
bits
of
the
address
are
saved. A
cache
entry
consists of
16
bytes of
data,
along
with
18
bits
of key
data
and
one valid bit.
During a
CPU
read cycle,
the
address is
compared
to
the
address in
the
key in
the
one location
where
that
data
could
be
stored.
If
the
address matches,
and
the
MMU is satisfied
or
shut
off,
the
cache
data
memories drive
the
data
directly
to
the
CPU.
If
the
cache misses,
the
associated
hardware
will
start
a
bus
cycle
to
read four long words,
and
fill one line of
the
cache.
Functional Description
77
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