With MMU Off
When
the
MMU
is
turned
off,
the
cache key alone determines
whether
any given processor read
cycle
can
hit
the
cache
or
must
go
to
main
memory.
The
bottom
512 Mbytes
of
address space
is
not
cached.
The
remaining 3.5
Gbytes
of
space
are
cached.
With MMU
On
When
the
MMU
is
on,
the
TLB
and
the
cache key are accessed in parallel.
If
the
TLB
has a
match,
then
the
cache may continue; otherwise,
the
MMU performs a
table
walk
to
find
the
translation.
On
the
next
try,
the
TLB
tag
and
cache key
are
checked again; obviously
the
tag
will have a hit,
and
if
the
cache
has
a
hit
it
can
supply
data
to
the
CPU.
Otherwise
the
hardware
will perform a cache fill cycle.
Only
the
bottom
16 Mbytes
of
address space
cannot
be
cached.
The
rernaining 4080 Mbytes
can
be
cached if desired.
It
is controlled by
the
Cache
Inhibit
bit
in
the
page
table
entry. Note:
the
CI
bit
only inhibits reading
data
into
the
cache; it does
not
inhibit
hits
on
data
that
is
already
stored
there.
Virtual Cache
The
cache is virtual, so
it
requires purging
after
translation
table
changes
or
after
DMA
to
memory.
Translation
table
changes cause
virtual
addresses
to
no longer represent
their
former
constituent
system lines. Because
of
the
virtual
cache, monitoring
of
DMA accesses
to
au-
tomatically invalidate cache
data
would require prohibitively long reverse address
translation.
Therefore
the
operating
systelns are responsible for clearing
the
cache
after
every DMA,
or
else
DMAing only
to
cache-inhibited pages.
The
cache has
separate
user
and
supervisor valid bits.
Any
particular
cache line could contain invalid
data,
valid supervisor
data,
or
valid user
data.
Each half is
automatically
selectively cleared on a write
to
the
corresponding
root
pointer.
This
allows software selective purging
of
the
user
and
supervisor
portions
of
the
cache.
More information
can
be
referenced in these manuals:
• MC68020 Users Manual (09826-90073).
• MC68881
Users Manual.
•
HP
9000 Series 300 Model 330/350 Accessory Designer's Guide (98562-90010).
Boot ROM and Self-Test LEOs
A
Boot
ROM
(actually two chips) whose
instructions
are executed by
the
CPU
shortly
after
power
up
is
used on
this
processor
board.
Test LEDs are visible
through
the
front cover slots. Different
patterns
of
onn
and
off
(Is
and
Os)
correspond
to
binary
or
hexadecimal
error
codes. These codes help you find
out
what's
working
and
what
is
not.
Chapter
4 provides
an
in-depth
explanation
of
the
Boot
ROM
functions.
Chapter
5 explains
the
error
codes
and
other
troubleshooting
processes.
78 Functional Description
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