Service
Model
83522A
If the EXTIMTR ALC INPUT circuits are suspected, select the desired mode
and supply a test signal (low-level DC or sine wave) in the front panel BNC
connector, and trace it through U6B at
A4TP15.
NOTE
Remove any tape applied to edge connector pins in the
previous procedure.
Detector Leg @ @
The "Detector Leg" of the ALC loop includes components between the Detector
Selection Switch and the Error Summing
Amplifier U3D.
Before troubleshooting the Detector Leg, be sure the Detector and Detector
Selection Switch are working correctly. See above.
The Detector Leg can be effectively tested by using the Open Loop method of
troubleshooting. This procedure utilizes the external leveling mode
EXT
by
supplying an external DC voltage or sine wave to the
EXTIMTR ALC INPUT
connector. This method breaks the ALC loop and allows waveforms to be
checked against known test signals. See Figure 8-33 (above the schematic
diagram).
Modulator Leg @ @
The "Modulator Leg" includes the Error Sample
&
Hold and the Main ALC
Amp.
U3D is a non-inverting unity-gain summing amplifier. Under leveled
conditions, both TP4 and TP7 should be nearly 0.0 Vdc. Under any conditions,
TP4 and TP7 should be at the same voltage. If not, suspect
U3D, 43, or the
Sample
&
Hold Driver.
U11 forms an inverting integrator. When TP7 is positive, TP6 should be at -0.6
Vdc. If not, suspect U2D or
U11. When TP7 is negative, TP6 should be at +7.5
Vdc. If this is not the case, suspect U11.
The following procedure can be used to check U3D and U11:
1.
Set power for -2
dBm at any CW frequency.
2. Press
83522A
rtxr
ALC.
3. Ground
A4TP
1
1.
4. To check
U3D, monitor TP4 and TP7 while adjusting the
EXTIMTR ALC
CAL
knob between the extremes of its range. Both
TP4 and TP7 should vary between approximately
i-0.5 and -0.5
Vdc.
5.
Verify
U11 by adjusting the
CAL
knob as described above and
monitoring TP6. Since
U11 is an integrator, TP6 should saturate
and clamp (due to
VR4) at -0.6 Vdc and i-7.5 Vdc, respectively.
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