Model
83522A
Table
of
Contents
ILLUSTRATIONS
(Cont'd)
Figure Page Figure Page
ALC Adjustments Test Setup
..........
5-26
ALC Adjustments Location
...........
5-27
Internal Leveling Adjustment
Setup
.............................
5-29
Internal Leveling Adjustments
Location
..........................
5-30
.........
Power Calibration Test Setup 5-31
Power Calibration Adjustment
..........................
Location 5-32
Power Meter Leveling Calibration
.....
5-33
Power Meter Leveling
Adjustment Location
..............
5-34
ALC Gain Adjustment Test
Setup
.............................
5-35
ALC Gain Adjustment Location
......
5-36
Power Sweep Test Setup
..............
5-37
Power Sweep Adjustment
Location
..........................
5-38
Test Setup for FM Driver
Adjustments
......................
5-39
A5
FM Driver Adjustment Location
...
5-40
FM Flatness Tolerance. DC to MHz
...
5-42
Marker Adjustments Test Setup
.......
5-43
Marker Adjustments on A8
...........
5-44
Marker Envelope
....................
5-45
50 MHz Birdie
......................
5-45
Marker Adjustments on A7
...........
5-45
On/Off Pulse of Correctly
Adjusted Circuit
...................
5-46
On/Off Pulse of Misadjusted
Circuit Showing Overlap
...........
5-46
External Marker Adjustments
Test Setup
........................
5-47
External Marker Adjustments
Location
..........................
5-48
Major Mechanical Parts
..............
6-2 1
Attaching Hardware
..................
6-23
Cables in
RF
Section
.................
6-27
RF
Output Connector J1
Exploded View
....................
6-28
Schematic Diagram Notes
.............
8-3
Hex Data Rotation Write
.
Bit Pattern
.........................
8-8
Hex Address Fast Read
.
Timing Diagram
...................
8-8
Hex Entry Keys
.......................
8-9
Module Exchange Procedure
..........
8-1 0
Rear Panel Connector
Alignment Diagram
...............
8-1 1
83522A RF Plug-in Simplified
Block Diagram
....................
8-25
83522A RF Plug-in Overall
....................
Block Diagram 8-25
.................
Display Test Pattern 8-26
A1 Front PanelIA2 Front Panel
...........
Interface. Block Diagram 8-31
A1 Front Panel. Component
.........................
Locations 8-31
A2 Front Panel Interface. Component
.............
Locations. Front View 8-31
A2 Front Panel Interface. Component
..............
Locations. Rear View 8-31
....................
Column Strobing 8-31
...................
RPG Pulse Trains 8-31
.................
YO Drive V (A2TP1) 8-31
Frequency
Tracking Voltage
..........................
(A2TP3) 8-31
............................
lV/GHz 8-31
A1 Front PanelIA2 Front Panel Inter-
...........
face. Schematic Diagram 8-31
...
A3
Digital Interface. Block Diagram
8-35
A3
Digital Interface. Component
.........................
Locations 8-35
Interval Timer Self-Test
..................
Timing Diagram 8-35
Major Address Decoder Self-Test
..................
Timing Diagram 8-35
A3
Digital Interface.
................
Schematic Diagram 8-35
.......
Simplified ALC Block Diagram 8-36
Typical ALC Troubleshooting
.............................
Setup 8-37
..........
Power Meter Leveling Setup 8-38
......
Simplified Modulator Schematic 8-43
..............
A4 ALC. Block Diagram 8-45
.......
A4 ALC. Component Locations 8-45
Retrace Blanking Waveform
..........
8-45
............
ALC DAC Test Waveform 8-45
................
Open Loop Procedure 8-45
...............
Open Loop Waveforms 8-45
A4 ALC. Schematic Diagram
.........
8-45
Plot of FM Coil Response Versus
.............
Modulation Frequency 8-46
A5
Address Decoder Timing
.......................
Waveforms 8-48
Power Sweep DAC Self-Test
........................
Waveform 8-50
........
A5
FM Driver. Block Diagram
8-51
...
A5
FM Driver. Component Locations
8-51
........
A5
Troubleshooting Test Setup 8-51
.......
A5
Troubleshooting Waveforms 8-51
A5
FM Driver. Schematic
..........................
Diagram 8-51