Chapter 2 2-9
HP ESA Status Registers
Using the Analyzer Status Registers
To query the status byte register, send the command *STB? The
response will be the decimal sum of the bits which are set to 1. For
example, if bit number 7 and bit number 3 are set to 1, the decimal sum
of the 2 bits is 128 plus 8. So the decimal value 136 is returned.
The status byte service request enable register lets you choose which
bits in the Status Byte Register will trigger a service request. Send the
Bit Description
0, 1 These bits are always set to 0.
2 A 1 in this bit position indicates that the SCPI error queue is not empty. The SCPI error
queue contains at least one error message.
3 A 1 in this bit position indicates that the questionable status summary bit has been set.
The questionable status event register can then be read to determine the specific
condition that caused this bit to be set.
4
A 1 in this bit position indicates that the analyzer has data ready in the output queue.
There are no lower status groups that provide input to this bit.
5 A 1 in this bit position indicates that the standard event status summary bit has been
set. The standard event status register can then be read to determine the specific event
that caused this bit to be set.
6
A 1 in this bit position indicates that the analyzer has at least one reason to report a
status change. This bit is also called the master summary status bit (MSS).
7 A 1 in this bit position indicates that the operation status summary bit has been set. The
operation status event register can then be read to determine the specific event that
caused this bit to be set.
Bit Number 76543210
Standard Event Status Summary Bit
Message Available (MAV)
Questionable Summary BitStatus
Error/Event Queue Summary Bit
Unused
Request Service (RQS) Summary Bit
Description
Operation S Summary Bittatus
Unused
ck764a
Status Byte Register
*STB?
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