HP ESA-E Series - Page 52

2-22 Chapter2
HP ESA Status Registers
Using the Analyzer Status Registers
Questionable Status Power event enable register
The Questionable Status Power Condition Register contains the
following bits:
Figure 2-9
Bit Description
0 Reserved. These bits are not used by the analyzer, but are for
future use with other HP products.
1 A 1 in this bit position indicates that the source (tracking
generator) output is unlevelled.
2 A 1 in this bit position indicates that the local oscillator (LO) in
the source (tracking generator) is unlevelled.
3 A 1 in this bit position indicates that the analyzer local oscillator
(LO) is unlevelled.
4 A 1 in this bit position indicates that the 50 MHz amplitude
reference signal is unlevelled.
5 Reserved. These bits are not used by the analyzer, but are for
future use with other HP products.
6 A1 in this bit position indicates that the input overload protection
(HP ESA models E4401B and E4411B only) is tripped.
7 A 1 in this bit position indicates that the first local osillator (LO)
output is unlevelled.
8–14 Unused. These bits are always set to 0.
15 Always Zero (0).
Bit Number
7
89101112131415
6
5
432
1
0
Reserved
50 MHz Osc Unleveled
LO Unleveled
Source LO Unleveled
Source Unleveled
Reserved
Unused
Unused
Unused
Unused
Unused
LO Out Unleveled
Unused
Unused
Input Overload Tripped
Description
Always Zero (0)
ck770a
Questionable Power Condition RegisterStatus
STATus:QUEStionable:POWer:CONDition?