+AO-9
+AEN
~
-lOW
-lOR
-DACK2
~
+T/C
+RESET
+DRQ2
~
+IRQ6
(Adapter Input, Load: 1 74LS)
These ten lines form an address
bus
by which a
register
is
selected to receive or supply the byte
transferred via lines DO-7. Bit 0
is
the low-order bit.
(Adapter Input, Load: 1 74LS)
The content
of
lines
AO-9
is
ignored if this line is
active.
(Adapter Input, Load: 1 74 LS)
The content
of
lines
DO-
7 is stored in the register
addressed by lines
AO-9
or
DACK2
at the trailing
edge
of
this signal.
(Adapter Input, Load: 1 74LS)
The content of the register addressed by lines
AO-9
or
DACK2
is
gated onto lines
DO-7
when this line
is
active.
(Adapter Input, Load: 2 74LS)
This line active degates output
DRQ2,
selects the
FDC
data register
as
the source/destination
of
bus
DO-
7, and indirectly gates T / C to IRQ6.
(Adapter Input, Load: 4 74 LS)
This line and
DACK2
active indicates that the byte
of data for which the
DMA
count was initialized
is
now being transferred.
(Adapter Input, Load: 1 74LS)
An
up level aborts any operation in process and
clears the Digital Output Register (DOR).
(Adapter Output, Driver: 74LS 3-state)
This line
is
made active when the attachment
is
ready
to transfer a byte
of
data to or from main storage. The
line is made inactive by
DACK2
becoming active or
an
I/O
read
of
the
FDC
data register.
(Adapter Output, Driver: 74LS 3-state)
This line
is
made active when the
FDC
has com-
pleted an operation.
It
results in an interrupt to a
routine which should examine the
FDC
result bytes
to reset the line and determine the ending condition.
2-105
To Next Page
Loading...
Need help?
General
