INS8250
Functional Pin Description
The following describes the function
of
all INS8250 input/output pins.
Some
of
these descriptions reference internal circuits.
Note: In the following descriptions, a low represents a logic 0 (0 volt
,.-......,
nominal) and a high represents a logic 1
(+2.4
volts nominal).
Input
Signals
Chip Select
(SCO,
CS1, CS2), Pins 12-14: When
CSO
and
CSI
are high
and CS2
is
low, the chip
is
selected. Chip selection
is
complete when
the decoded chip select signal
is
latched with an active (low) Address
Strobe (ADS) input. This enable comunication between the INS8250
and the CPU.
Data Input Strobe (DISTRDISTR) Pins
22
and
21:
When
DISTR
is
high or
DISTR
is low while the chip
is
selected, allows the
CPU
to read
status information
or
data from a selected register
of
the INS8250.
Note: Only an active
DISTR
or
DISTR
input
is
required to transfer
data from the INS8250 during a read operation. Therefore, tie either
the
DISTR
input permanently low or the
DISTR
input permanently
high, if not used.
,.-......,
Data
Output
Strobe
(DOSTR,
DOSTR),
Pins
19
and
18:
When
DOSTR
is
high
or
DOSTR
is
low while the chip
is
selected, allows the
CPU
to write data or control words into a selected register
of
the
INS8250.
Note: Only an active
DOSTR
or
DOSTR
input
is
required to transfer
data to the INS8250 during a write operation. Therefore, tie either the
DPSTR
input permanently low or the
DOSTR
input permanently high,
if not used.
Address Strobe
(ADS),
Pin 25: When low, provides latching for the
Register Select
(AO,
AI,
A2) and Chip Select (SOC,
CSl,
CS2)
signals.
Note:
An
active
ADS
input is required when the Register Select
(AO,
AI,
A2) signals are not stable for the duration
of
a read or write
operation.
If
not required, the ADS input permanently low.
2-129
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