Bit 0: This bit is the receiver
Data
Ready (DR) indicator. Bit 0 is set to a
logic 1 whenever a complete incoming character has been received and
transferred into the Receiver Buffer Register. Bit 0 may be reset to a
logic 0 either by the
CPU
reading the data
in
the Receiver Buffer
Register
or
by writing a logic 0 into it from the
CPU.
Bit
1:
This bit is the Overrun Error
(OE)
indicator. Bit 1 indicates that
r--...
data in the Receiver Buffer Register was not read by the
CPU
before the
next character was transferred into the Receiver Buffer Register,
thereby destroying the previous character. The
OE
indicator
is
reset
whenever the
CPU
reads the contents
of
the Line Status Register.
Bit 2: This bit
is
the Parity Error (PE) indicator. Bit 2 indicates that
the received data character does not have the correct even or odd parity,
as selected by the even parity-select bit. the
PE
bit
is
set to a logic 1
upon detection
of
a parity error and is reset to a logic 0 whenever the
CPU
reads the contents
of
the Line Status Register.
Bit 3:This bit is the Framing Error
(FE)
indicator. Bit 3 indicates that
the received character did not have a valid Stop bit. Bit 3
is
set
to
a logic
1 whenever the Stop bit following the last data bit or parity
bit
is
detected as a zero bit (Spacing level).
Bit 4: This bit is the Break Interrupt (BI) indicator. Bit 4 is set to a logic
1 whenever the received data input is held in the Spacing (logic 0) state
r--...
for longer than a full word transmission time (that is, the total time
of
Start bit + data bits + Parity + Stop bits).
Note: Bits 1 through 4 are the error conditions that produce a Receiver
Line Status interrupt whenever any
of
the corresponding conditions
are detected.
Bit 5: This bit
is
the Transmitter Holding Register Empty
(THRE)
indicator. Bit 5 indicates that the INS8250
is
ready to accept a new
character for transmission.
In
addition, this bit causes the INS8250 to
issue an interrupt to the
CPU
when the Transmit Holding Register
Empty Interrupt enable
is
set high. The
THRE
bit
is
set to a logic 1
when a character
is
transferred from the Transmitter Holding Register
into the Transmitter Shift Register. The bit
is
reset to logic 0
concurrently with the loading
of
the Transmitter Holding Register by
the CPU.
Bit 6: This bit
is
the Transmitter Shift Register Empty (TSRE)
indicator. Bit 6 is set
to
a logic 1 whenever the Transmitter Shift
Register
is
idle.
It
is
reset to logic 0 upon a data transfer from the
Tranmitter Holding Register to the Transmitter Shift Register. Bit 6
is
a read-only bit.
Bit 7: This bit
is
permanently set to logic
O.
2-138
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