The processor is supported by a set
of
high function support devices
providing four channels
of
20-bit Direct Memory Access (DMA),
three 16-bit timer counter channels, and eight prioritized
interrupt levels.
Three
of
the four
DMA
channels are available
on
the
I/O
bus and are
provided to support high speed data transfers between
I/O
devices and
memory without processor intervention. The fourth
DMA
channel
is
programmed to refresh the system dynamic memory. This
is
done by
programming a channel
of
the timer counter device to periodically
request a dummy
DMA
transfer. This creates a memory read cycle
which
is
available to refresh dynamic storage both on the System Board
and in the System Expansion slots. All
DMA
data transfers, except the
refresh channel, take five processor clocks
of
210
ns
or
1.
05 ns if the
processor ready line is not deactivated. Refresh
DMA
cycles take four
clocks or 840 ns.
The three timer/counters are used by the system as follows: Channel 0
is
used to time and request refresh cycles from the
DMA
channel,
Channel 2 is used to support the tone generation for the audio speaker,
and Channel 1 is used by the system as a general purpose timer
providing a constant time base for implementing a time-of-day clock.
Each channel has a minimum timing resolution
of
1.05
f.Lsec.
Of
the eight prioritized levels ofinterrupt, six are bussed to the
I/O
slots
for use by feature cards. Two levels are used on the System Board.
Level 0, the highest priority,
is
attached to
Channell
of
the timer
counter and provides a periodic interrupt. Level 1 is attached to the
keyboard adapter circuits and receives an interrupt for each scan code
sent by the keyboard. The Non-Maskable Interrupt
(NMI)
of
the 8088
is used to report memory parity errors.
The System Board is designed to support both
ROM
and Read/Write
Memory. The System Board contains space for
48K
x 8
of
ROM
or
EPROM.
Six module sockets are provided, each capable
of
accepting
an
8K
x 8 device. Five
of
the sockets are populated with 40 KB
of
ROM. This
ROM
contains the Cassette BASIC interpreter, cassette
operating system, Power-on Self-test,
I/O
drivers, dot patterns for 128
characters inn graphics mode, and a diskette bootstrap loader. The
ROM
is
packaged in 24-pin modules and has an access time
of
250
ns
and a cycle time
of
375 ns.
The System Board also contains from
16K
x 9 to
64K
x 9
of
Read/
Write Memory. A minimum system would have 16 KB
of
memory with
module sockets for an additional 48 KB. In a cassette version
of
the
system, approximately 4 KB
is
used by the system leaving approxi-
mately 12 KB
of
user's space for BASIC programs. Additional
memory beyond the System Board's maximum
of64
KB,
is
obtained by
adding memory cards in the System Expansion slots.
2-4
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