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IBM 7090 - Page 30

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3.1.
06
Program
Register
(PR)
(Systems
3.04.00.1-3.04.03.1)
The
program
register
is
a
ten-position
trigger
register
whose
positions
are
labeled
(S),
(1-9).
The
program
register
receives
the
operation
code
of
the
instruction
directly
from
the
storage
bus
and
holds
the
operation
code
throughout
the
execution
of
the
instruc-
tion.
The
output
of
the
program
register
is
decoded
to
initiate
and
control
the
CPU
so
it
will
execute
the
instruction.
Positions
(1-5)
contain
the
primary
operation
part
of
the
operation
code;
positions
(6-9)
cOlltain
the
secondary
part.
3.1.07
Shift
Counter
(SC)
(Systems
3.04.14.1-3.04.19.1)
The
shift
counter
(SC)
is
an
eight-position,
count-down
counter.
The
SC
counts
the
number
of
shifts
taken
during
a
shift
operation
and
is
also
used
as
part
of
the
decoder
for
operations
that
have
a
primary
operation
code
of
76.
See
Section
5.00.00.
Figure
3.
l-SB
is
a
reproduction
of
an
ALD
page
without
the
reset
lines,
but
with
special
terms
applied
to
blocks
or
combinations
of
blocks.
Because
the
SC
is
a
step-down
counter,
a
number
must
be
set
in
the
counter
at
the
start
of
the
operation.
The
address
switches
are
gated
to
set
the
SC.
Considering
a
shift
of
seven,
the
"+ P AS
to
SC"
line
to
positions
15,
16,
and
17
will
be
active.
This
condition
causes
one
trigger
(A
or
B)
in
each
position,
to
latch
on,
thereby
indicating
a 1
in
the
three
positions.
\Vith
"AS
17
to
SC
17"
active,
the
,tOR
circuits
at
3F
and
3H
are
conditioned,
indi-
cating
that
trigger
B
will
latch
on
and
trigger
A
will
be
in
a
preset
condition.
The
in-
phase
output
of
the
+OR
at
3F
conditions
the
A
trigger
of
position
16,
along
with
"AS 16
to
SC
16."
The
out-of-phase
line
of
the
+OR
at
3F
deconditions
trigger
B.
Now
positions
16
and
17
have
a
bit.
Position
15
has
both
triggers
preset
by
"AS 15
to
SC
15."
Because
the
SC
is
not
being
stepped
at
this
time,
trigger
B
of
position
15
will
latch
on.
The
SC
is
divided
into
groups
of
two
for
lookahead
operations.
The
outputs
of
each
group
are
AND'ed
together
to
determine
if
the
higher
order
positions
are
to
be
stepped.
The
high-order
position
of
each
group
have
a
line,
"-
N
SC
set
gate,
"
to
prevent
an
error
if
a
number
other
than
seven
is
set
in
the
SC.
Suppose
a 1
is
in
the
AS;
this
sets
trig-
ger
B
of
position
17.
The
in-phase
output
of
the
+OR
at
3F
will
condition
one
leg
of
the
+ AND
at
4D,
as
this
in-phase
output
did
previously.
Because
position
16
trigger
B
is
off,
the
out-of-phase
output
of
the
+OR
at
3B
is
plus.
With
trigger
B
of
position
16
off
(not
turned
on
yet
because
of
circuit
delays),
the
out-of-phase
output
of
trigger
B
is
also
plus.
Normally,
this
output
would
condition
the
preset
AND
circuit
at
4C
and
the
A
trig-
ger
of
position
16
would
turn
on.
The
turning
on
of
the
A
trigger
of
position
16
is
pre-
vented
by
"-
N
SC
set
gate,
"
which
deconditions
the
circuit
at
4C
whenever
the
AS
is
gated
to
the
SC.
A 70
ns
pulse,
generated
by
the
CP
set
pulse,
steps
the
SC.
When
in
automatic,
the
SC
is
stepped
every
clock
pluse
until
reaching
zero.
The
"+N
step
SC
17"
and
"-N
step
SC
17"
are
generated
by
the
same
pulse
and
will
be
active
at
the
same
time
.•
These
two
lines
condition
triggers
A
and
B
of
position
17.
Because
trigger
B
of
position
17
is
on,
the
minus
step
pulse
to
the
+AND
at
4F
will
turn
off.
Because
trigger
B
of
position
16
is
in
the
preset
condition,
it
will
latch
on
with
the
out-of-phase
output
of
position
17
go-
ing
positive.
Position
15
will
not
be
affected
because
the
step
control
circuits
are
not
conditioned.
Both
triggers
A
and
B
of
position
17
are
off,
with
trigger
A
preset.
Both
positions
15
and
16
have
trigger
B on
and
the
SC
value
is
now
six.
29

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