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IBM 7090 - Page 31

IBM 7090
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The
next
step
pulse
(2nd)
latches
on
the
A
trigger
of
position
17.
The
in-phase
out-
put
of
the
+
AND
at
4R
conditions
the
+OR
at
3F.
presetting
trigger
B
of
position
17.
The
out-of-phase
output
of
the
+OR
at
3F
goes
minus
and
causes
trigger
B of
position
16
to
turn
off.
Because
the
A
trigger
was
not
preset,
both
triggers
in
position
16
will
be
off
at
the
end of
the
step
pulse.
After
the
step
pulse,
however,
trigger
B
will
be
preset.
Trigger
A
of
position
17
can
stay
on
only
for
the
duration
of
the
step
pulse.
When
the
step
pulse
ends,
the
6S
uuf
capacitor
at
2R
keeps
the
output
of
the
preset
AND
circuit
active
long
enough
to
allow
trigger
A
to
latch
on.
At
the
end
of
this
step
pulse
(2nd),
the
SC
contains
a
5.
The
next
step
pulse
turns
off
position
17,
and
only
trigger
B
of
SC
15
is
on.
The
SC
is
now 4.
Step
control
circuits
now
allow
positions
15
and
17
to
receive
the
next
step
pulse.
This
step
pulse
will
turn
off
position
15 by
deconditioning
the
AND
circuit
that
corre-
sponds
to
4F
in
Figure
3.
l-SB
(Systems
03.04.16.1
for
actual
circuit).
The
B
trigger
of
position
17
and
the
A
trigger
of
position
16
are
latched
on.
The
SC
will
continue
to
step
down
until
it
reaches
zero.
Figure
3.
I-SA
is
a
timing
chart
that
shows
the
stepping
of
the
SC.
The
solid
lines
indicate
the
latched
condition,
while
the
dotted
lines
indicate
a
preset
condition.
3.1.
OS
Program
Counter
(PC)
(Systems
3.05.00.1-3.05.07.1)
The
program
counter
(PC)
is
a
16-position
count-up
counter.
The
high-order
position,
PC2,
is
used
to
signal
that
all
addresses
in
core
have
been
set
to
zero,
on
the
clear
operation
only.
The
remaining
positions,
3
through
17,
indicate
the
location
of
the
next
instruction
to
be
executed
by
the
CPU
when
it
is
operating
sequentially.
Figure
3.
1-9B
is
a
reproduction
of
an
ALD
page
without
the
reset
lines,
and
with
special
terms
applied
to
blocks
or
combinations
of
blocks.
The
step
of
the
PC
is
generated
on
Systems
03.05.
OS.
1. Two
lines,
"-N
STP
PC
17"
and
liN
minus
to
STP
PC
17.
II
are
generated
by
+-N
advance
PC
CNTR."
These
two
lines
are
active
whenever
PC
is
stepped.
With
the
PC
set
to
zero,
a
step
pulse
will
advance
the
PC
to
one.
To do
so,
the
step
pulse
AND's
with
the
out-of-phase
output
of
trigger
B
of
position
17 (now off),
to
condi-
tion
the
AND
circuit
at
4R.
The
+A
at
4R
presets
trigger
A
of
PC17.
Trigger
A
remains
preset
until
the
step
pulse
falls
(becomes
positive),
and
then
trig-
ger
A
latches
on. A
capacitor
holds
the
preset
condition
until
the
latching
action
takes
place.
With
trigger
A
latched
on,
its
output
conditions
the
-POR
at
3G
as
well
as
the
+OR
at
3R,
signaling
a 1
in
PC17.
With
the
+OR
at
3G
conditioned,
its
in-phase
output
presets
trigger
B
of
PC17.
The
in-phase
output
of
3G
also
presets
the
+AND
at
4D,
which
in
turn
presets
trigger
A
of
position
16.
The
next
step
pulse
will
reset
trigger
A
and
latch
trigger
B
of
PC17.
After
the
step
pulse,
trigger
B of
PC17
goes
off.
With
the
PC17
trigger
off,
its
out-of-phase
output
becomes
plus,
conditioning
the
+AND
at
4E,
which
latches
trigger
A
of
PC16.
The
+OR
at
3C
is
conditioned,
presetting
trigger
B
of
PC16.
The
output
of
the
+OR
at
3C
also
30

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