9.1.6 Multiword DMA timings
The Multiword DMA timing meets Mode 2 of the ATA/ATAPI-5 description.
WRITE DATA
READ DATA
DMACK-
DMARQ
DIOR-/DIOW-
t0
tL
tJ
tI tD
tK
tFtG
tH
tG
tZ
CS0-/CS1-
tM
tN
25–DMACK- to read data releasedtZ
–10CS (1:0) holdtN
–
25
CS (1:0) valid to DIOR–/DIOW–tM
35–DIOR-/DIOW- to DMARQ– delaytL
–25DIOR-/DIOW- negated pulse widthtK
–5DIOR-/DIOW- to DMACK- holdtJ
–0DMACK- to –DIOR/–DIOW setuptI
–10DIOW- data holdtH
–20DIOR-/DIOW– data setuptG
–5DIOR- data holdtF
–50DIOR- data accesstE
–70DIOR-, DIOW- asserted pulse widthtD
–120Cycle timet0
MAX. (ns)MIN. (ns)Parameter descriptions
Figure 26. Multiword DMA cycle timings
Deskstar 60 GXP Hard disk drive specification
31